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19 commits

Author SHA1 Message Date
Nikolaj Schlej
a19aeadb54 Revert "Update hexadecimal numbers output format from ABCDh to 0xABCD" due to breaking downstream tools
This reverts commit 9cc9518f8b.
2025-04-26 19:09:49 +07:00
Nikolaj Schlej
9cc9518f8b Update hexadecimal numbers output format from ABCDh to 0xABCD 2025-04-26 16:16:02 +07:00
Nikolaj Schlej
a824260064 Add MX77L12850F 2025-02-13 01:09:48 +01:00
Nikolaj Schlej
214b356f84 Add AMIC A25LQ64 to internal JEDEC ID database 2025-02-12 08:50:50 +01:00
William Leara
166c797a20 add Micron XM25RH128C
Add support for the Micron XM25RH128C SPI flash part.  This is a 128Mb part with DevID0 = 0x43, and DevID1 = 0x18.
2023-10-24 22:15:42 -07:00
Nikolaj Schlej
934ce1f3f8 Kaitai-based Intel ACM and BootGuard parsers
As the first step towards automated parsing, this change set replaces outdated BootGuard-related parsers with shiny new KaitaiStruct-based ones.
It also does the following:
- improves Intel FIT definitions by using the relevant specification
- adds sha1, sha384, sha512 and sm3 digest implementations
- updates LZMA SDK to v22.01
- moves GUIDs out of include files to prevent multiple instantiations
- enforces C++11
- adds Kaitai-based parsers for Intel FIT, BootGuard v1 and BootGuard v2 structures
- makes many small refactorings here, there and everywhere
2022-09-10 13:14:29 +02:00
Nikolaj Schlej
4006954bc1 Downcast all qtsizetype to UINT32 manually, apply consistent identation 2022-08-28 12:47:01 +02:00
Nikolaj Schlej
74910c4658 Add support for Intel ME FPT header version 2.1 2022-08-25 08:54:34 +02:00
Nikolai Kostrigin
d1e47539fc
common/descriptor.cpp: add JEDEC ID C86015 definition as GD25LQ16V ()
"parseIntelImage: SPI flash with unknown JEDEC ID C86015 found in VSCC table"
message was displayed on a device equipped with GigaDevice GD25LQ16V SPI flash

Co-authored-by: Nikolai Kostrigin <nickel@altlinux.org>
2021-02-17 19:51:34 +03:00
Nikolai SAOUKH
57e4d6dfa0 Update AMIC Technology spi flash info
Info taken from http://www.amictechnology.com/english/flash_spi_flash.html
2020-07-16 10:03:42 +03:00
vit9696
f074dfc5ca More SPI chips (thx 4.8.4) 2018-12-11 14:51:26 +03:00
vit9696
4f6efe5195 Add more chip IDs, thank you Google 2018-06-02 19:27:24 +03:00
Alex Matrosov
e3ace324ee bugfix 2018-04-29 22:33:19 -07:00
Alex Matrosov
82a89b2c03 multiple fixes 2018-01-23 00:00:03 -08:00
Alex Matrosov
63088afd87 A45
+ FFSv3 support with large files and large sections
+ proper names for Flash Descriptor v2 regions ()
+ better alignment calculations ()
+ improved NVRAM parser
+ post IBB hash support for Boot Guard
+  bugfixes
+ companion tool updated
2017-12-10 17:56:00 -08:00
Cr4sh
0f0bc32a42 NE Alpha 40 2017-02-14 09:39:16 +03:00
Alex Matrosov
cb430456bf NE Alpha 33
- human readable JEDEC ID
- NVRAM parser separated from FFS parser
- added support for LZMAF86 sections
- solved a bug with parsing of VSS variables with invalid sizes
2016-10-09 23:05:04 -07:00
Nikolaj Schlej
2024c1898b NE A21: deQtization begins
- added FfsBuilder code and UI, but reconstruction routines for volumes,
files and sections are still not ready
- FfsOps moved to common
- QVector and QPair aren't used anymore, replaces with std::vector and
std::pair
- common classes are now independent from QObject
- next step is to replace QString with CBString from bstrlib
2016-03-01 08:20:44 +01:00
Nikolaj Schlej
2e788a8a1a Big structure update
- files split into common and app-specific ones
- messages from parser and finder separated
- ffsEngine split into multiple classes to reduce complexity
- still no image rebuild
2015-04-02 10:04:37 +02:00
Renamed from descriptor.cpp (Browse further)