mirror of
https://github.com/LongSoft/UEFITool.git
synced 2025-05-12 22:26:13 -04:00
Small fixes of FLASH_DESCRIPTOR_REGION_SECTION definition
This commit is contained in:
parent
8a14965463
commit
e5cf61f89a
2 changed files with 51 additions and 55 deletions
46
descriptor.h
46
descriptor.h
|
@ -43,7 +43,7 @@ typedef struct _FLASH_DESCRIPTOR_MAP {
|
|||
UINT32 : 5;
|
||||
// FLMAP 1
|
||||
UINT32 MasterBase : 8;
|
||||
UINT32 NumberOfMasters : 2;
|
||||
UINT32 NumberOfMasters : 2; // Zero-based number of flash masters
|
||||
UINT32 : 6;
|
||||
UINT32 PchStrapsBase : 8;
|
||||
UINT32 NumberOfPchStraps : 8; // One-based number of UINT32s to read as PCH straps, min=0, max=255 (1 Kb)
|
||||
|
@ -113,32 +113,28 @@ typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION_V2 {
|
|||
// All base and limit register are storing upper part of actual UINT32 base and limit
|
||||
// If limit is zero - region is not present
|
||||
typedef struct _FLASH_DESCRIPTOR_REGION_SECTION {
|
||||
UINT32 :32;
|
||||
UINT16 Region0Base; // BIOS
|
||||
UINT16 Region0Limit; //
|
||||
UINT16 Region1Base; // ME
|
||||
UINT16 Region1Limit; //
|
||||
UINT16 Region2Base; // GbE
|
||||
UINT16 Region2Limit; //
|
||||
UINT16 Region3Base; // PDR
|
||||
UINT16 Region3Limit; //
|
||||
UINT16 Region4Base; // Reserved region
|
||||
UINT16 Region4Limit; //
|
||||
UINT16 Region5Base; // Reserved region
|
||||
UINT16 Region5Limit; //
|
||||
UINT16 Region6Base; // Reserved region
|
||||
UINT16 Region6Limit; //
|
||||
UINT16 Region7Base; // Reserved region
|
||||
UINT16 Region7Limit; //
|
||||
UINT16 Region8Base; // EC
|
||||
UINT16 Region8Limit; //
|
||||
UINT16 DescriptorBase; // Descriptor
|
||||
UINT16 DescriptorLimit; //
|
||||
UINT16 BiosBase; // BIOS
|
||||
UINT16 BiosLimit; //
|
||||
UINT16 MeBase; // ME
|
||||
UINT16 MeLimit; //
|
||||
UINT16 GbeBase; // GbE
|
||||
UINT16 GbeLimit; //
|
||||
UINT16 PdrBase; // PDR
|
||||
UINT16 PdrLimit; //
|
||||
UINT16 Region5Base; // Reserved region
|
||||
UINT16 Region5Limit; //
|
||||
UINT16 Region6Base; // Reserved region
|
||||
UINT16 Region6Limit; //
|
||||
UINT16 Region7Base; // Reserved region
|
||||
UINT16 Region7Limit; //
|
||||
UINT16 Region8Base; // Reserved region
|
||||
UINT16 Region8Limit; //
|
||||
UINT16 EcBase; // EC
|
||||
UINT16 EcLimit; //
|
||||
} FLASH_DESCRIPTOR_REGION_SECTION;
|
||||
|
||||
// Flash block erase sizes
|
||||
#define FLASH_BLOCK_ERASE_SIZE_4KB 0x0000
|
||||
#define FLASH_BLOCK_ERASE_SIZE_8KB 0x0001
|
||||
#define FLASH_BLOCK_ERASE_SIZE_64KB 0x000F
|
||||
|
||||
// Master section
|
||||
typedef struct _FLASH_DESCRIPTOR_MASTER_SECTION {
|
||||
UINT16 BiosId;
|
||||
|
|
|
@ -282,9 +282,9 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
|
|||
QByteArray me;
|
||||
UINT32 meBegin = 0;
|
||||
UINT32 meEnd = 0;
|
||||
if (regionSection->Region1Limit) {
|
||||
meBegin = calculateRegionOffset(regionSection->Region1Base);
|
||||
meEnd = calculateRegionSize(regionSection->Region1Base, regionSection->Region1Limit);
|
||||
if (regionSection->MeLimit) {
|
||||
meBegin = calculateRegionOffset(regionSection->MeBase);
|
||||
meEnd = calculateRegionSize(regionSection->MeBase, regionSection->MeLimit);
|
||||
me = intelImage.mid(meBegin, meEnd);
|
||||
meEnd += meBegin;
|
||||
}
|
||||
|
@ -292,9 +292,9 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
|
|||
QByteArray bios;
|
||||
UINT32 biosBegin = 0;
|
||||
UINT32 biosEnd = 0;
|
||||
if (regionSection->Region0Limit) {
|
||||
biosBegin = calculateRegionOffset(regionSection->Region0Base);
|
||||
biosEnd = calculateRegionSize(regionSection->Region0Base, regionSection->Region0Limit);
|
||||
if (regionSection->BiosLimit) {
|
||||
biosBegin = calculateRegionOffset(regionSection->BiosBase);
|
||||
biosEnd = calculateRegionSize(regionSection->BiosBase, regionSection->BiosLimit);
|
||||
|
||||
// Check for Gigabyte specific descriptor map
|
||||
if (biosEnd - biosBegin == (UINT32)intelImage.size()) {
|
||||
|
@ -316,9 +316,9 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
|
|||
QByteArray gbe;
|
||||
UINT32 gbeBegin = 0;
|
||||
UINT32 gbeEnd = 0;
|
||||
if (regionSection->Region2Limit) {
|
||||
gbeBegin = calculateRegionOffset(regionSection->Region2Base);
|
||||
gbeEnd = calculateRegionSize(regionSection->Region2Base, regionSection->Region2Limit);
|
||||
if (regionSection->GbeLimit) {
|
||||
gbeBegin = calculateRegionOffset(regionSection->GbeBase);
|
||||
gbeEnd = calculateRegionSize(regionSection->GbeBase, regionSection->GbeLimit);
|
||||
gbe = intelImage.mid(gbeBegin, gbeEnd);
|
||||
gbeEnd += gbeBegin;
|
||||
}
|
||||
|
@ -326,9 +326,9 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
|
|||
QByteArray pdr;
|
||||
UINT32 pdrBegin = 0;
|
||||
UINT32 pdrEnd = 0;
|
||||
if (regionSection->Region3Limit) {
|
||||
pdrBegin = calculateRegionOffset(regionSection->Region3Base);
|
||||
pdrEnd = calculateRegionSize(regionSection->Region3Base, regionSection->Region3Limit);
|
||||
if (regionSection->PdrLimit) {
|
||||
pdrBegin = calculateRegionOffset(regionSection->PdrBase);
|
||||
pdrEnd = calculateRegionSize(regionSection->PdrBase, regionSection->PdrLimit);
|
||||
pdr = intelImage.mid(pdrBegin, pdrEnd);
|
||||
pdrEnd += pdrBegin;
|
||||
}
|
||||
|
@ -337,9 +337,9 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
|
|||
UINT32 ecBegin = 0;
|
||||
UINT32 ecEnd = 0;
|
||||
if (descriptorVersion == 2) {
|
||||
if (regionSection->Region8Limit) {
|
||||
pdrBegin = calculateRegionOffset(regionSection->Region8Base);
|
||||
pdrEnd = calculateRegionSize(regionSection->Region8Base, regionSection->Region8Limit);
|
||||
if (regionSection->EcLimit) {
|
||||
pdrBegin = calculateRegionOffset(regionSection->EcBase);
|
||||
pdrEnd = calculateRegionSize(regionSection->EcBase, regionSection->EcLimit);
|
||||
pdr = intelImage.mid(ecBegin, ecEnd);
|
||||
ecEnd += ecBegin;
|
||||
}
|
||||
|
@ -434,23 +434,23 @@ UINT8 FfsEngine::parseIntelImage(const QByteArray & intelImage, QModelIndex & in
|
|||
|
||||
// Check regions presence once again
|
||||
QVector<UINT32> offsets;
|
||||
if (regionSection->Region2Limit) {
|
||||
if (regionSection->GbeLimit) {
|
||||
offsets.append(gbeBegin);
|
||||
info += tr("\nGbE region offset: %1h").hexarg(gbeBegin);
|
||||
}
|
||||
if (regionSection->Region1Limit) {
|
||||
if (regionSection->MeLimit) {
|
||||
offsets.append(meBegin);
|
||||
info += tr("\nME region offset: %1h").hexarg(meBegin);
|
||||
}
|
||||
if (regionSection->Region0Limit) {
|
||||
if (regionSection->BiosLimit) {
|
||||
offsets.append(biosBegin);
|
||||
info += tr("\nBIOS region offset: %1h").hexarg(biosBegin);
|
||||
}
|
||||
if (regionSection->Region3Limit) {
|
||||
if (regionSection->PdrLimit) {
|
||||
offsets.append(pdrBegin);
|
||||
info += tr("\nPDR region offset: %1h").hexarg(pdrBegin);
|
||||
}
|
||||
if (descriptorVersion == 2 && regionSection->Region8Limit) {
|
||||
if (descriptorVersion == 2 && regionSection->EcLimit) {
|
||||
offsets.append(ecBegin);
|
||||
info += tr("\nEC region offset: %1h").hexarg(ecBegin);
|
||||
}
|
||||
|
@ -2813,17 +2813,17 @@ UINT8 FfsEngine::reconstructIntelImage(const QModelIndex& index, QByteArray& rec
|
|||
const FLASH_DESCRIPTOR_MAP* descriptorMap = (const FLASH_DESCRIPTOR_MAP*)(descriptor.constData() + sizeof(FLASH_DESCRIPTOR_HEADER));
|
||||
const FLASH_DESCRIPTOR_REGION_SECTION* regionSection = (const FLASH_DESCRIPTOR_REGION_SECTION*)calculateAddress8((const UINT8*)descriptor.constData(), descriptorMap->RegionBase);
|
||||
QByteArray gbe;
|
||||
UINT32 gbeBegin = calculateRegionOffset(regionSection->Region2Base);
|
||||
UINT32 gbeEnd = gbeBegin + calculateRegionSize(regionSection->Region2Base, regionSection->Region2Limit);
|
||||
UINT32 gbeBegin = calculateRegionOffset(regionSection->GbeBase);
|
||||
UINT32 gbeEnd = gbeBegin + calculateRegionSize(regionSection->GbeBase, regionSection->GbeLimit);
|
||||
QByteArray me;
|
||||
UINT32 meBegin = calculateRegionOffset(regionSection->Region1Base);
|
||||
UINT32 meEnd = meBegin + calculateRegionSize(regionSection->Region1Base, regionSection->Region1Limit);
|
||||
UINT32 meBegin = calculateRegionOffset(regionSection->MeBase);
|
||||
UINT32 meEnd = meBegin + calculateRegionSize(regionSection->MeBase, regionSection->MeLimit);
|
||||
QByteArray bios;
|
||||
UINT32 biosBegin = calculateRegionOffset(regionSection->Region0Base);
|
||||
UINT32 biosEnd = biosBegin + calculateRegionSize(regionSection->Region0Base, regionSection->Region0Limit);
|
||||
UINT32 biosBegin = calculateRegionOffset(regionSection->BiosBase);
|
||||
UINT32 biosEnd = biosBegin + calculateRegionSize(regionSection->BiosBase, regionSection->BiosLimit);
|
||||
QByteArray pdr;
|
||||
UINT32 pdrBegin = calculateRegionOffset(regionSection->Region3Base);
|
||||
UINT32 pdrEnd = pdrBegin + calculateRegionSize(regionSection->Region3Base, regionSection->Region3Limit);
|
||||
UINT32 pdrBegin = calculateRegionOffset(regionSection->PdrBase);
|
||||
UINT32 pdrEnd = pdrBegin + calculateRegionSize(regionSection->PdrBase, regionSection->PdrLimit);
|
||||
QByteArray ec;
|
||||
UINT32 ecBegin = 0;
|
||||
UINT32 ecEnd = 0;
|
||||
|
@ -2836,8 +2836,8 @@ UINT8 FfsEngine::reconstructIntelImage(const QModelIndex& index, QByteArray& rec
|
|||
}
|
||||
else if (componentSection->FlashParameters.ReadClockFrequency == FLASH_FREQUENCY_17MHZ) { // Skylake+ descriptor
|
||||
descriptorVersion = 2;
|
||||
ecBegin = calculateRegionOffset(regionSection->Region8Base);
|
||||
ecEnd = ecBegin + calculateRegionSize(regionSection->Region8Base, regionSection->Region8Limit);
|
||||
ecBegin = calculateRegionOffset(regionSection->EcBase);
|
||||
ecEnd = ecBegin + calculateRegionSize(regionSection->EcBase, regionSection->EcLimit);
|
||||
}
|
||||
else {
|
||||
msg(tr("reconstructIntelImage: unknown descriptor version with ReadClockFrequency %1h").hexarg(componentSection->FlashParameters.ReadClockFrequency));
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue