mirror of
https://github.com/LongSoft/UEFITool.git
synced 2025-05-13 14:44:47 -04:00
Port of latest descriptor handling changes from master
- added Skylake+ descriptor format support
This commit is contained in:
Nikolaj Schlej
parent
d36951da88
commit
b8317ac4f2
4 changed files with 240 additions and 92 deletions
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@ -216,18 +216,19 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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const FLASH_DESCRIPTOR_MAP* descriptorMap = (const FLASH_DESCRIPTOR_MAP*)(descriptor + sizeof(FLASH_DESCRIPTOR_HEADER));
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const FLASH_DESCRIPTOR_UPPER_MAP* upperMap = (const FLASH_DESCRIPTOR_UPPER_MAP*)(descriptor + FLASH_DESCRIPTOR_UPPER_MAP_BASE);
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const FLASH_DESCRIPTOR_REGION_SECTION* regionSection = (const FLASH_DESCRIPTOR_REGION_SECTION*)calculateAddress8(descriptor, descriptorMap->RegionBase);
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const FLASH_DESCRIPTOR_MASTER_SECTION* masterSection = (const FLASH_DESCRIPTOR_MASTER_SECTION*)calculateAddress8(descriptor, descriptorMap->MasterBase);
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const FLASH_DESCRIPTOR_COMPONENT_SECTION* componentSection = (const FLASH_DESCRIPTOR_COMPONENT_SECTION*)calculateAddress8(descriptor, descriptorMap->ComponentBase);
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// GbE region
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QByteArray gbe;
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UINT32 gbeBegin = 0;
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UINT32 gbeEnd = 0;
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if (regionSection->GbeLimit) {
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gbeBegin = calculateRegionOffset(regionSection->GbeBase);
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gbeEnd = calculateRegionSize(regionSection->GbeBase, regionSection->GbeLimit);
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gbe = intelImage.mid(gbeBegin, gbeEnd);
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gbeEnd += gbeBegin;
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// Check descriptor version by getting hardcoded value of FlashParameters.ReadClockFrequency
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UINT8 descriptorVersion = 0;
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if (componentSection->FlashParameters.ReadClockFrequency == FLASH_FREQUENCY_20MHZ) // Old descriptor
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descriptorVersion = 1;
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else if (componentSection->FlashParameters.ReadClockFrequency == FLASH_FREQUENCY_17MHZ) // Skylake+ descriptor
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descriptorVersion = 2;
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else {
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msg(tr("parseIntelImage: unknown descriptor version with ReadClockFrequency %1h").hexarg(componentSection->FlashParameters.ReadClockFrequency));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// ME region
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QByteArray me;
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UINT32 meBegin = 0;
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@ -238,16 +239,7 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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me = intelImage.mid(meBegin, meEnd);
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meEnd += meBegin;
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}
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// PDR region
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QByteArray pdr;
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UINT32 pdrBegin = 0;
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UINT32 pdrEnd = 0;
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if (regionSection->PdrLimit) {
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pdrBegin = calculateRegionOffset(regionSection->PdrBase);
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pdrEnd = calculateRegionSize(regionSection->PdrBase, regionSection->PdrLimit);
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pdr = intelImage.mid(pdrBegin, pdrEnd);
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pdrEnd += pdrBegin;
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}
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// BIOS region
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QByteArray bios;
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UINT32 biosBegin = 0;
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@ -273,7 +265,43 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// GbE region
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QByteArray gbe;
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UINT32 gbeBegin = 0;
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UINT32 gbeEnd = 0;
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if (regionSection->GbeLimit) {
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gbeBegin = calculateRegionOffset(regionSection->GbeBase);
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gbeEnd = calculateRegionSize(regionSection->GbeBase, regionSection->GbeLimit);
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gbe = intelImage.mid(gbeBegin, gbeEnd);
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gbeEnd += gbeBegin;
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}
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// PDR region
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QByteArray pdr;
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UINT32 pdrBegin = 0;
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UINT32 pdrEnd = 0;
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if (regionSection->PdrLimit) {
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pdrBegin = calculateRegionOffset(regionSection->PdrBase);
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pdrEnd = calculateRegionSize(regionSection->PdrBase, regionSection->PdrLimit);
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pdr = intelImage.mid(pdrBegin, pdrEnd);
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pdrEnd += pdrBegin;
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}
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// EC region
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QByteArray ec;
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UINT32 ecBegin = 0;
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UINT32 ecEnd = 0;
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if (descriptorVersion == 2) {
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if (regionSection->EcLimit) {
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pdrBegin = calculateRegionOffset(regionSection->EcBase);
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pdrEnd = calculateRegionSize(regionSection->EcBase, regionSection->EcLimit);
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pdr = intelImage.mid(ecBegin, ecEnd);
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ecEnd += ecBegin;
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}
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}
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// Check for intersections between regions
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// Descriptor
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if (hasIntersection(descriptorBegin, descriptorEnd, gbeBegin, gbeEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, descriptor region has intersection with GbE region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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@ -290,6 +318,11 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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msg(tr("parseIntelImage: descriptor parsing failed, descriptor region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(descriptorBegin, descriptorEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, descriptor region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// GbE
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if (hasIntersection(gbeBegin, gbeEnd, meBegin, meEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, GbE region has intersection with ME region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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@ -302,6 +335,11 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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msg(tr("parseIntelImage: descriptor parsing failed, GbE region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(gbeBegin, gbeEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, GbE region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// ME
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if (hasIntersection(meBegin, meEnd, biosBegin, biosEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, ME region has intersection with BIOS region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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@ -310,23 +348,36 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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msg(tr("parseIntelImage: descriptor parsing failed, ME region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(meBegin, meEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, ME region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// BIOS
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if (hasIntersection(biosBegin, biosEnd, pdrBegin, pdrEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, BIOS region has intersection with PDR region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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if (descriptorVersion == 2 && hasIntersection(biosBegin, biosEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, BIOS region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// PDR
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if (descriptorVersion == 2 && hasIntersection(pdrBegin, pdrEnd, ecBegin, ecEnd)) {
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msg(tr("parseIntelImage: descriptor parsing failed, PDR region has intersection with EC region"));
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return ERR_INVALID_FLASH_DESCRIPTOR;
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}
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// Region map is consistent
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// Intel image
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QString name = tr("Intel image");
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QString info = tr("Full size: %1h (%2)\nFlash chips: %3\nRegions: %4\nMasters: %5\nPCH straps: %6\nPROC straps: %7\nICC table entries: %8")
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QString info = tr("Full size: %1h (%2)\nFlash chips: %3\nRegions: %4\nMasters: %5\nPCH straps: %6\nPROC straps: %7")
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.hexarg(intelImage.size()).arg(intelImage.size())
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.arg(descriptorMap->NumberOfFlashChips + 1) //
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.arg(descriptorMap->NumberOfRegions + 1) // Zero-based numbers in storage
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.arg(descriptorMap->NumberOfMasters + 1) //
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.arg(descriptorMap->NumberOfPchStraps)
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.arg(descriptorMap->NumberOfProcStraps)
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.arg(descriptorMap->NumberOfIccTableEntries);
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.arg(descriptorMap->NumberOfProcStraps);
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// Construct parsing data
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pdata.fixed = TRUE;
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@ -363,31 +414,67 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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}
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// Region access settings
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info += tr("\nRegion access settings:");
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info += tr("\nBIOS:%1%2h ME:%3%4h GbE:%5%6h")
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.hexarg2(masterSection->BiosRead, 2)
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.hexarg2(masterSection->BiosWrite, 2)
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.hexarg2(masterSection->MeRead, 2)
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.hexarg2(masterSection->MeWrite, 2)
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.hexarg2(masterSection->GbeRead, 2)
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.hexarg2(masterSection->GbeWrite, 2);
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if (descriptorVersion == 1) {
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const FLASH_DESCRIPTOR_MASTER_SECTION* masterSection = (const FLASH_DESCRIPTOR_MASTER_SECTION*)calculateAddress8(descriptor, descriptorMap->MasterBase);
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info += tr("\nRegion access settings:");
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info += tr("\nBIOS:%1h %2h ME:%3h %4h GbE:%5h %6h")
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.hexarg2(masterSection->BiosRead, 2)
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.hexarg2(masterSection->BiosWrite, 2)
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.hexarg2(masterSection->MeRead, 2)
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.hexarg2(masterSection->MeWrite, 2)
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.hexarg2(masterSection->GbeRead, 2)
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.hexarg2(masterSection->GbeWrite, 2);
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// BIOS access table
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info += tr("\nBIOS access table:");
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info += tr("\n Read Write");
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info += tr("\nDesc %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_DESC ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_DESC ? "Yes " : "No ");
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info += tr("\nBIOS Yes Yes");
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info += tr("\nME %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_ME ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_ME ? "Yes " : "No ");
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info += tr("\nGbE %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_GBE ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_GBE ? "Yes " : "No ");
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info += tr("\nPDR %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ");
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// BIOS access table
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info += tr("\nBIOS access table:");
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info += tr("\n Read Write");
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info += tr("\nDesc %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_DESC ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_DESC ? "Yes " : "No ");
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info += tr("\nBIOS Yes Yes");
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info += tr("\nME %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_ME ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_ME ? "Yes " : "No ");
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info += tr("\nGbE %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_GBE ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_GBE ? "Yes " : "No ");
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info += tr("\nPDR %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ");
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}
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else if (descriptorVersion == 2) {
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const FLASH_DESCRIPTOR_MASTER_SECTION_V2* masterSection = (const FLASH_DESCRIPTOR_MASTER_SECTION_V2*)calculateAddress8(descriptor, descriptorMap->MasterBase);
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info += tr("\nRegion access settings:");
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info += tr("\nBIOS: %1h %2h ME: %3h %4h\nGbE: %5h %6h EC: %7h %8h")
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.hexarg2(masterSection->BiosRead, 3)
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.hexarg2(masterSection->BiosWrite, 3)
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.hexarg2(masterSection->MeRead, 3)
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.hexarg2(masterSection->MeWrite, 3)
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.hexarg2(masterSection->GbeRead, 3)
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.hexarg2(masterSection->GbeWrite, 3)
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.hexarg2(masterSection->EcRead, 3)
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.hexarg2(masterSection->EcWrite, 3);
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// BIOS access table
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info += tr("\nBIOS access table:");
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info += tr("\n Read Write");
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info += tr("\nDesc %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_DESC ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_DESC ? "Yes " : "No ");
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info += tr("\nBIOS Yes Yes");
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info += tr("\nME %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_ME ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_ME ? "Yes " : "No ");
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info += tr("\nGbE %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_GBE ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_GBE ? "Yes " : "No ");
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info += tr("\nPDR %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_PDR ? "Yes " : "No ");
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info += tr("\nEC %1 %2")
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.arg(masterSection->BiosRead & FLASH_DESCRIPTOR_REGION_ACCESS_EC ? "Yes " : "No ")
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.arg(masterSection->BiosWrite & FLASH_DESCRIPTOR_REGION_ACCESS_EC ? "Yes " : "No ");
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}
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// VSCC table
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const VSCC_TABLE_ENTRY* vsccTableEntry = (const VSCC_TABLE_ENTRY*)(descriptor + ((UINT16)upperMap->VsccTableBase << 4));
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@ -430,6 +517,11 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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QModelIndex pdrIndex;
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result = parsePdrRegion(pdr, pdrBegin, index, pdrIndex);
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}
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// Parse EC region
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else if (descriptorVersion == 2 && offsets.at(i) == ecBegin) {
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QModelIndex ecIndex;
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result = parseEcRegion(ec, ecBegin, index, ecIndex);
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}
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if (result)
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return result;
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}
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@ -445,6 +537,8 @@ STATUS FfsParser::parseIntelImage(const QByteArray & intelImage, const UINT32 pa
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IntelDataEnd = biosEnd;
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else if (LastRegionOffset == pdrBegin)
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IntelDataEnd = pdrEnd;
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else if (descriptorVersion == 2 && LastRegionOffset == ecBegin)
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IntelDataEnd = ecEnd;
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if (IntelDataEnd > (UINT32)intelImage.size()) { // Image file is truncated
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msg(tr("parseIntelImage: image size %1 (%2) is smaller than the end of last region %3 (%4), may be damaged")
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@ -613,6 +707,31 @@ STATUS FfsParser::parsePdrRegion(const QByteArray & pdr, const UINT32 parentOffs
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return ERR_SUCCESS;
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}
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STATUS FfsParser::parseEcRegion(const QByteArray & ec, const UINT32 parentOffset, const QModelIndex & parent, QModelIndex & index)
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{
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// Check sanity
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if (ec.isEmpty())
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return ERR_EMPTY_REGION;
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// Get parent's parsing data
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PARSING_DATA pdata = parsingDataFromQModelIndex(parent);
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// Get info
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QString name = tr("EC region");
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QString info = tr("Full size: %1h (%2)").
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hexarg(ec.size()).arg(ec.size());
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// Construct parsing data
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pdata.fixed = TRUE;
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pdata.offset += parentOffset;
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if (pdata.isOnFlash) info.prepend(tr("Offset: %1h\n").hexarg(pdata.offset));
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// Add tree item
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index = model->addItem(Types::Region, Subtypes::PdrRegion, name, QString(), info, QByteArray(), ec, parsingDataToQByteArray(pdata), parent);
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return ERR_SUCCESS;
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}
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STATUS FfsParser::parseBiosRegion(const QByteArray & bios, const UINT32 parentOffset, const QModelIndex & parent, QModelIndex & index)
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{
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// Sanity check
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