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UT 0.21.0
- added support for new Intel descriptor type, based on [this](http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1f7fd720c81755144423f2d4062c39cc651adc0a) coreboot commit, thanks to lordkag for issue #32 - solved a bug with incorrect volume free space item placement during volume replace, now works as expected - solved an issue with incorrect Aptio capsule parsing introduced in 0.20.8
This commit is contained in:
Nikolaj Schlej
parent
9c4ddbec62
commit
aa80837bf5
7 changed files with 309 additions and 126 deletions
131
descriptor.h
131
descriptor.h
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@ -17,7 +17,7 @@ WITHWARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#include "basetypes.h"
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// Make sure we use right packing rules
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#pragma pack(push,1)
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#pragma pack(push, 1)
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// Flash descriptor header
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typedef struct _FLASH_DESCRIPTOR_HEADER {
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@ -34,37 +34,38 @@ typedef struct _FLASH_DESCRIPTOR_HEADER {
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// Descriptor map
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// Base fields are storing bits [11:4] of actual base addresses, all other bits are 0
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typedef struct _FLASH_DESCRIPTOR_MAP {
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UINT8 ComponentBase; // 0x03 on most machines
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UINT8 NumberOfFlashChips; // Zero-based number of flash chips installed on board
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UINT8 RegionBase; // 0x04 on most machines
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UINT8 NumberOfRegions; // Zero-based number of flash regions (descriptor is always included)
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UINT8 MasterBase; // 0x06 on most machines
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UINT8 NumberOfMasters; // Zero-based number of flash masters
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UINT8 PchStrapsBase; // 0x10 on most machines
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UINT8 NumberOfPchStraps; // One-based number of UINT32s to read as PCH Straps, min=0, max=255 (1 Kb)
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UINT8 ProcStrapsBase; // 0x20 on most machines
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UINT8 NumberOfProcStraps; // Number of PROC straps to be read, can be 0 or 1
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UINT8 IccTableBase; // 0x21 on most machines
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UINT8 NumberOfIccTableEntries; // 0x00 on most machines
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UINT8 DmiTableBase; // 0x25 on most machines
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UINT8 NumberOfDmiTableEntries; // 0x00 on most machines
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UINT16 ReservedZero; // Still unknown, zeros in all descriptors I have seen
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// FLMAP0
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UINT32 ComponentBase : 8;
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UINT32 NumberOfFlashChips : 2; // Zero-based number of flash chips installed on board
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UINT32 : 6;
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UINT32 RegionBase : 8;
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UINT32 : 8;
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// FLMAP 1
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UINT32 MasterBase : 8;
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UINT32 NumberOfMasters : 2;
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UINT32 : 6;
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UINT32 PchStrapsBase : 8;
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UINT32 NumberOfPchStraps : 8; // One-based number of UINT32s to read as PCH straps, min=0, max=255 (1 Kb)
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// FLMAP 2
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UINT32 ProcStrapsBase : 8;
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UINT32 NumberOfProcStraps : 8; // One-based number of UINT32s to read as processor straps, min=0, max=255 (1 Kb)
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UINT32: 16;
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} FLASH_DESCRIPTOR_MAP;
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// Component section
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// Flash parameters DWORD structure
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typedef struct _FLASH_PARAMETERS {
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UINT8 FirstChipDensity : 3;
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UINT8 SecondChipDensity : 3;
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UINT8 ReservedZero0 : 2; // Still unknown, zeros in all descriptors I have seen
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UINT8 ReservedZero1 : 8; // Still unknown, zeros in all descriptors I have seen
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UINT8 ReservedZero2 : 4; // Still unknown, zeros in all descriptors I have seen
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UINT8 FirstChipDensity : 4;
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UINT8 SecondChipDensity : 4;
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UINT8 : 8;
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UINT8 : 1;
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UINT8 ReadClockFreqency : 3; // Hardcoded value of 20 Mhz (000b) in v1 descriptors and 17 Mhz (110b) in v2 ones
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UINT8 FastReadEnabled : 1;
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UINT8 FastReadFreqency : 3;
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UINT8 FlashReadStatusFrequency : 3;
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UINT8 FlashWriteFrequency : 3;
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UINT8 DualOutputFastReadSupported : 1;
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UINT8 ReservedZero3 : 1; // Still unknown, zero in all descriptors I have seen
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UINT8 : 1;
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} FLASH_PARAMETERS;
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// Flash densities
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@ -74,11 +75,16 @@ typedef struct _FLASH_PARAMETERS {
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#define FLASH_DENSITY_4MB 0x03
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#define FLASH_DENSITY_8MB 0x04
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#define FLASH_DENSITY_16MB 0x05
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#define FLASH_DENSITY_32MB 0x06
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#define FLASH_DENSITY_64MB 0x07
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#define FLASH_DENSITY_UNUSED 0x0F
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// Flash frequencies
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#define FLASH_FREQUENCY_20MHZ 0x00
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#define FLASH_FREQUENCY_33MHZ 0x01
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#define FLASH_FREQUENCY_50MHZ 0x04
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#define FLASH_FREQUENCY_20MHZ 0x00
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#define FLASH_FREQUENCY_33MHZ 0x01
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#define FLASH_FREQUENCY_48MHZ 0x02
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#define FLASH_FREQUENCY_50MHZ_30MHZ 0x04
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#define FLASH_FREQUENCY_17MHZ 0x06
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// Component section structure
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typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION {
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@ -87,24 +93,45 @@ typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION {
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UINT8 InvalidInstruction1; //
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UINT8 InvalidInstruction2; //
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UINT8 InvalidInstruction3; //
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UINT16 PartitionBoundary; // Upper 16 bit of partition boundary address. Default is 0x0000, which makes the boundary to be 0x00001000
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UINT16 ReservedZero; // Still unknown, zero in all descriptors I have seen
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} FLASH_DESCRIPTOR_COMPONENT_SECTION;
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// Component section structure
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typedef struct _FLASH_DESCRIPTOR_COMPONENT_SECTION_V2 {
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FLASH_PARAMETERS FlashParameters;
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UINT8 InvalidInstruction0; // Instructions for SPI chip, that must not be executed, like FLASH ERASE
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UINT8 InvalidInstruction1; //
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UINT8 InvalidInstruction2; //
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UINT8 InvalidInstruction3; //
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UINT8 InvalidInstruction4; //
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UINT8 InvalidInstruction5; //
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UINT8 InvalidInstruction6; //
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UINT8 InvalidInstruction7; //
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} FLASH_DESCRIPTOR_COMPONENT_SECTION_V2;
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// Region section
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// All base and limit register are storing upper part of actual UINT32 base and limit
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// If limit is zero - region is not present
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typedef struct _FLASH_DESCRIPTOR_REGION_SECTION {
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UINT16 ReservedZero; // Still unknown, zero in all descriptors I have seen
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UINT16 :16;
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UINT16 FlashBlockEraseSize; // Size of block erased by single BLOCK ERASE command
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UINT16 BiosBase;
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UINT16 BiosLimit;
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UINT16 MeBase;
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UINT16 MeLimit;
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UINT16 GbeBase;
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UINT16 GbeLimit;
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UINT16 PdrBase;
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UINT16 PdrLimit;
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UINT16 Region0Base; // BIOS
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UINT16 Region0Limit; //
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UINT16 Region1Base; // ME
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UINT16 Region1Limit; //
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UINT16 Region2Base; // GbE
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UINT16 Region2Limit; //
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UINT16 Region3Base; // PDR
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UINT16 Region3Limit; //
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UINT16 Region4Base; // Reserved region
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UINT16 Region4Limit; //
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UINT16 Region5Base; // Reserved region
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UINT16 Region5Limit; //
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UINT16 Region6Base; // Reserved region
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UINT16 Region6Limit; //
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UINT16 Region7Base; // Reserved region
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UINT16 Region7Limit; //
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UINT16 Region8Base; // EC
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UINT16 Region8Limit; //
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} FLASH_DESCRIPTOR_REGION_SECTION;
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// Flash block erase sizes
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@ -115,24 +142,40 @@ typedef struct _FLASH_DESCRIPTOR_REGION_SECTION {
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// Master section
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typedef struct _FLASH_DESCRIPTOR_MASTER_SECTION {
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UINT16 BiosId;
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UINT8 BiosRead;
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UINT8 BiosWrite;
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UINT8 BiosRead;
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UINT8 BiosWrite;
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UINT16 MeId;
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UINT8 MeRead;
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UINT8 MeWrite;
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UINT8 MeRead;
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UINT8 MeWrite;
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UINT16 GbeId;
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UINT8 GbeRead;
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UINT8 GbeWrite;
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UINT8 GbeRead;
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UINT8 GbeWrite;
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} FLASH_DESCRIPTOR_MASTER_SECTION;
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// Master section v2 (Skylake+)
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typedef struct _FLASH_DESCRIPTOR_MASTER_SECTION_V2 {
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UINT32 : 8;
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UINT32 BiosRead : 12;
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UINT32 BiosWrite : 12;
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UINT32 : 8;
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UINT32 MeRead : 12;
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UINT32 MeWrite : 12;
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UINT32 : 8;
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UINT32 GbeRead : 12;
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UINT32 GbeWrite : 12;
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UINT32 :32;
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UINT32 : 8;
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UINT32 EcRead : 12;
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UINT32 EcWrite : 12;
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} FLASH_DESCRIPTOR_MASTER_SECTION_V2;
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// Region access bits in master section
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#define FLASH_DESCRIPTOR_REGION_ACCESS_DESC 0x01
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#define FLASH_DESCRIPTOR_REGION_ACCESS_BIOS 0x02
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#define FLASH_DESCRIPTOR_REGION_ACCESS_ME 0x04
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#define FLASH_DESCRIPTOR_REGION_ACCESS_GBE 0x08
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#define FLASH_DESCRIPTOR_REGION_ACCESS_PDR 0x10
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//!TODO: Describe PCH and PROC straps sections, as well as ICC and DMI tables
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#define FLASH_DESCRIPTOR_REGION_ACCESS_EC 0x20
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// Base address of descriptor upper map
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#define FLASH_DESCRIPTOR_UPPER_MAP_BASE 0x0EFC
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