mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-06-03 08:08:39 -04:00
git subrepo clone --force --branch=exo2 https://github.com/m4xw/emummc
subrepo: subdir: "emummc" merged: "3791be9f" upstream: origin: "https://github.com/m4xw/emummc" branch: "exo2" commit: "3791be9f" git-subrepo: version: "0.4.1" origin: "???" commit: "???"
This commit is contained in:
Michael Scire
SciresM
parent
6c145d76c7
commit
f82954e98b
29 changed files with 1653 additions and 871 deletions
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@ -23,6 +23,10 @@ static const sclock_t _clock_i2c5 = {
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CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 0, 4 //81.6MHz -> 400KHz
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};
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static sclock_t _clock_sdmmc_legacy_tm = {
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CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, 1, 4, 66
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};
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void clock_enable(const sclock_t *clk)
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{
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// Put clock into reset.
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@ -34,6 +38,8 @@ void clock_enable(const sclock_t *clk)
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CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
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// Enable.
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CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
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usleep(2);
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// Take clock off reset.
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CLOCK(clk->reset) &= ~(1 << clk->index);
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}
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@ -56,6 +62,33 @@ void clock_disable_i2c5()
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clock_disable(&_clock_i2c5);
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}
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static void _clock_enable_pllc4()
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{
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if ((CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & (PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | 0xFFFFFF))
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== (PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | (104 << 8) | 4))
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return;
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// Enable Phase and Frequency lock detection.
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//CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = PLLC4_MISC_EN_LCKDET;
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// Disable PLL and IDDQ in case they are on.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLC4_BASE_IDDQ;
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(void)CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE);
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usleep(10);
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// Set PLLC4 dividers.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = (104 << 8) | 4; // DIVM: 4, DIVP: 1.
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// Enable PLLC4 and wait for Phase and Frequency lock.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) |= PLLCX_BASE_ENABLE;
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(void)CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE);
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & PLLCX_BASE_LOCK))
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;
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msleep(1); // Wait a bit for PLL to stabilize.
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}
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#define L_SWR_SDMMC1_RST (1 << 14)
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#define L_SWR_SDMMC2_RST (1 << 9)
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#define L_SWR_SDMMC4_RST (1 << 15)
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@ -194,57 +227,103 @@ static void _clock_sdmmc_clear_enable(u32 id)
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}
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}
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static u32 _clock_sdmmc_table[8] = { 0 };
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static void _clock_sdmmc_config_legacy_tm()
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{
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sclock_t *clk = &_clock_sdmmc_legacy_tm;
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if (!(CLOCK(clk->enable) & (1 << clk->index)))
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clock_enable(clk);
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}
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#define PLLP_OUT0 0x0
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typedef struct _clock_sdmmc_t
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{
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u32 clock;
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u32 real_clock;
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} clock_sdmmc_t;
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static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val)
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static clock_sdmmc_t _clock_sdmmc_table[4] = { 0 };
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#define SDMMC_CLOCK_SRC_PLLP_OUT0 0x0
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#define SDMMC_CLOCK_SRC_PLLC4_OUT2 0x3
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#define SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ 0x1
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static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
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{
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u32 divisor = 0;
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u32 source = PLLP_OUT0;
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u32 source = SDMMC_CLOCK_SRC_PLLP_OUT0;
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if (id > SDMMC_4)
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return 0;
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// Get IO clock divisor.
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switch (val)
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{
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case 25000:
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*pout = 24728;
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divisor = 31;
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*pclock = 24728;
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divisor = 31; // 16.5 div.
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break;
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case 26000:
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*pout = 25500;
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divisor = 30;
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*pclock = 25500;
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divisor = 30; // 16 div.
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break;
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case 40800:
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*pout = 40800;
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divisor = 18;
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*pclock = 40800;
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divisor = 18; // 10 div.
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break;
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case 50000:
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*pout = 48000;
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divisor = 15;
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*pclock = 48000;
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divisor = 15; // 8.5 div.
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break;
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case 52000:
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*pout = 51000;
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divisor = 14;
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*pclock = 51000;
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divisor = 14; // 8 div.
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break;
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case 100000:
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*pout = 90667;
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divisor = 7;
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source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
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*pclock = 99840;
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divisor = 2; // 2 div.
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break;
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case 164000:
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*pclock = 163200;
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divisor = 3; // 2.5 div.
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break;
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case 200000:
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*pout = 163200;
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divisor = 3;
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break;
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case 208000:
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*pout = 204000;
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divisor = 2;
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switch (id)
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{
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case SDMMC_1:
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source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
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break;
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case SDMMC_2:
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source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
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break;
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case SDMMC_3:
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source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
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break;
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case SDMMC_4:
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source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
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break;
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}
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*pclock = 199680;
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divisor = 0; // 1 div.
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break;
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default:
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*pout = 24728;
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divisor = 31;
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*pclock = 24728;
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divisor = 31; // 16.5 div.
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}
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_clock_sdmmc_table[2 * id] = val;
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_clock_sdmmc_table[2 * id + 1] = *pout;
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_clock_sdmmc_table[id].clock = val;
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_clock_sdmmc_table[id].real_clock = *pclock;
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// PLLC4 and LEGACY_TM clocks are already initialized,
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// because we init at the first eMMC read.
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// // Enable PLLC4 if in use by any SDMMC.
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// if (source)
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// _clock_enable_pllc4();
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// // Set SDMMC legacy timeout clock.
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// _clock_sdmmc_config_legacy_tm();
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// Set SDMMC clock.
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switch (id)
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{
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case SDMMC_1:
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@ -264,69 +343,75 @@ static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val)
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return 1;
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}
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void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val)
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void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val)
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{
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if (_clock_sdmmc_table[2 * id] == val)
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if (_clock_sdmmc_table[id].clock == val)
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{
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*pout = _clock_sdmmc_table[2 * id + 1];
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*pclock = _clock_sdmmc_table[id].real_clock;
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}
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else
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{
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int is_enabled = _clock_sdmmc_is_enabled(id);
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if (is_enabled)
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_clock_sdmmc_clear_enable(id);
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_clock_sdmmc_config_clock_source_inner(pout, id, val);
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_clock_sdmmc_config_clock_host(pclock, id, val);
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if (is_enabled)
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_clock_sdmmc_set_enable(id);
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_clock_sdmmc_is_reset(id);
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}
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}
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void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type)
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void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type)
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{
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// Get Card clock divisor.
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switch (type)
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{
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case 0:
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*pout = 26000;
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case SDHCI_TIMING_MMC_ID: // Actual IO Freq: 380.59 KHz.
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*pclock = 26000;
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*pdivisor = 66;
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break;
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case 1:
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*pout = 26000;
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case SDHCI_TIMING_MMC_LS26:
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*pclock = 26000;
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*pdivisor = 1;
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break;
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case 2:
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*pout = 52000;
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case SDHCI_TIMING_MMC_HS52:
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*pclock = 52000;
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*pdivisor = 1;
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break;
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case 3:
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case 4:
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case 11:
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*pout = 200000;
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case SDHCI_TIMING_MMC_HS200:
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case SDHCI_TIMING_MMC_HS400:
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case SDHCI_TIMING_UHS_SDR104:
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*pclock = 200000;
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*pdivisor = 1;
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break;
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case 5:
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*pout = 25000;
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case SDHCI_TIMING_SD_ID: // Actual IO Freq: 380.43 KHz.
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*pclock = 25000;
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*pdivisor = 64;
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break;
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case 6:
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case 8:
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*pout = 25000;
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case SDHCI_TIMING_SD_DS12:
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case SDHCI_TIMING_UHS_SDR12:
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*pclock = 25000;
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*pdivisor = 1;
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break;
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case 7:
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*pout = 50000;
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case SDHCI_TIMING_SD_HS25:
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case SDHCI_TIMING_UHS_SDR25:
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*pclock = 50000;
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*pdivisor = 1;
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break;
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case 10:
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*pout = 100000;
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case SDHCI_TIMING_UHS_SDR50:
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*pclock = 100000;
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*pdivisor = 1;
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break;
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case 13:
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*pout = 40800;
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case SDHCI_TIMING_UHS_SDR82:
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*pclock = 164000;
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*pdivisor = 1;
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break;
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case 14:
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*pout = 200000;
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case SDHCI_TIMING_UHS_DDR50:
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*pclock = 40800;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_MMC_DDR52: // Actual IO Freq: 49.92 MHz.
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*pclock = 200000;
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*pdivisor = 2;
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break;
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}
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@ -339,15 +424,15 @@ int clock_sdmmc_is_not_reset_and_enabled(u32 id)
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void clock_sdmmc_enable(u32 id, u32 val)
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{
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u32 div = 0;
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u32 clock = 0;
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if (_clock_sdmmc_is_enabled(id))
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_clock_sdmmc_clear_enable(id);
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_clock_sdmmc_set_reset(id);
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_clock_sdmmc_config_clock_source_inner(&div, id, val);
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_clock_sdmmc_config_clock_host(&clock, id, val);
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_clock_sdmmc_set_enable(id);
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_clock_sdmmc_is_reset(id);
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usleep((100000 + div - 1) / div);
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usleep((100000 + clock - 1) / clock);
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_clock_sdmmc_clear_reset(id);
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_clock_sdmmc_is_reset(id);
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}
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@ -35,12 +35,16 @@
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48
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#define CLK_RST_CONTROLLER_OSC_CTRL 0x50
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#define CLK_RST_CONTROLLER_PLLC_BASE 0x80
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#define CLK_RST_CONTROLLER_PLLC_OUT 0x84
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#define CLK_RST_CONTROLLER_PLLC_MISC 0x88
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#define CLK_RST_CONTROLLER_PLLC_MISC_1 0x8C
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#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
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#define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
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#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
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#define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
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#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
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#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8
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#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC
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#define CLK_RST_CONTROLLER_PLLX_BASE 0xE0
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#define CLK_RST_CONTROLLER_PLLX_MISC 0xE4
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#define CLK_RST_CONTROLLER_PLLE_BASE 0xE8
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@ -50,6 +54,7 @@
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#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM 0x110
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138
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#define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154
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@ -57,11 +62,13 @@
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 0x198
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 0x1B8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD 0x1C0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
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@ -95,9 +102,13 @@
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
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#define CLK_RST_CONTROLLER_RST_DEV_V_CLR 0x434
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
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#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
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#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450
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@ -108,16 +119,32 @@
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#define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
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#define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
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#define CLK_RST_CONTROLLER_PLLC4_BASE 0x5A4
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#define CLK_RST_CONTROLLER_PLLC4_MISC 0x5A8
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#define CLK_RST_CONTROLLER_PLLC_MISC_2 0x5D0
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#define CLK_RST_CONTROLLER_PLLC4_OUT 0x5E4
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#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 0x65C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL 0x66C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL 0x66C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
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#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
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#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710
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#define CLK_NO_SOURCE 0x0
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/*! PLL control and status bits */
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#define PLLCX_BASE_ENABLE (1 << 30)
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#define PLLCX_BASE_REF_DIS (1 << 29)
|
||||
#define PLLCX_BASE_LOCK (1 << 27)
|
||||
|
||||
#define PLLC4_MISC_EN_LCKDET (1 << 30)
|
||||
#define PLLC4_BASE_IDDQ (1 << 18)
|
||||
#define PLLC4_OUT3_CLKEN (1 << 1)
|
||||
#define PLLC4_OUT3_RSTN_CLR (1 << 0)
|
||||
|
||||
/*! Generic clock descriptor. */
|
||||
typedef struct _sclock_t
|
||||
{
|
||||
|
|
@ -136,8 +163,8 @@ void clock_disable(const sclock_t *clk);
|
|||
/*! Clock control for specific hardware portions. */
|
||||
void clock_enable_i2c5();
|
||||
void clock_disable_i2c5();
|
||||
void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
|
||||
void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type);
|
||||
void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val);
|
||||
void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type);
|
||||
int clock_sdmmc_is_not_reset_and_enabled(u32 id);
|
||||
void clock_sdmmc_enable(u32 id, u32 val);
|
||||
void clock_sdmmc_disable(u32 id);
|
||||
|
|
|
|||
|
|
@ -49,12 +49,17 @@ static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size)
|
|||
vu32 *base = (vu32 *)QueryIoMapping(i2c_addrs[I2C_5], 0x1000);
|
||||
base[I2C_CMD_ADDR0] = x << 1; //Set x (send mode).
|
||||
base[I2C_CMD_DATA1] = tmp; //Set value.
|
||||
base[I2C_CNFG] = (2 * size - 2) | 0x2800; //Set size and send mode.
|
||||
_i2c_wait(base); //Kick transaction.
|
||||
base[I2C_CNFG] = ((size - 1) << 1) | 0x2800; //Set size and send mode.
|
||||
_i2c_wait(base); //Kick transaction.
|
||||
|
||||
base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
|
||||
|
||||
u32 timeout = get_tmr_ms() + 1500;
|
||||
while (base[I2C_STATUS] & 0x100)
|
||||
;
|
||||
{
|
||||
if (get_tmr_ms() > timeout)
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (base[I2C_STATUS] << 28)
|
||||
return 0;
|
||||
|
|
@ -68,14 +73,18 @@ static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x)
|
|||
return 0;
|
||||
|
||||
vu32 *base = (vu32 *)QueryIoMapping(i2c_addrs[I2C_5], 0x1000);
|
||||
|
||||
base[I2C_CMD_ADDR0] = (x << 1) | 1; // Set x (recv mode).
|
||||
base[I2C_CNFG] = (size - 1) << 1 | 0x2840; // Set size and recv mode.
|
||||
_i2c_wait(base); // Kick transaction.
|
||||
base[I2C_CMD_ADDR0] = (x << 1) | 1; // Set x (recv mode).
|
||||
base[I2C_CNFG] = ((size - 1) << 1) | 0x2840; // Set size and recv mode.
|
||||
_i2c_wait(base); // Kick transaction.
|
||||
|
||||
base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
|
||||
|
||||
u32 timeout = get_tmr_ms() + 1500;
|
||||
while (base[I2C_STATUS] & 0x100)
|
||||
;
|
||||
{
|
||||
if (get_tmr_ms() > timeout)
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (base[I2C_STATUS] << 28)
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#define APBDEV_PMC_PWRGATE_TOGGLE 0x30
|
||||
#define APBDEV_PMC_PWRGATE_STATUS 0x38
|
||||
#define APBDEV_PMC_NO_IOPOWER 0x44
|
||||
#define PMC_NO_IOPOWER_SDMMC1_IO_EN (1 << 12)
|
||||
#define APBDEV_PMC_SCRATCH0 0x50
|
||||
#define APBDEV_PMC_SCRATCH1 0x54
|
||||
#define APBDEV_PMC_SCRATCH20 0xA0
|
||||
|
|
@ -37,6 +38,7 @@
|
|||
#define APBDEV_PMC_SCRATCH33 0x120
|
||||
#define APBDEV_PMC_SCRATCH40 0x13C
|
||||
#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
|
||||
#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000
|
||||
#define APBDEV_PMC_RST_STATUS 0x1B4
|
||||
#define APBDEV_PMC_IO_DPD_REQ 0x1B8
|
||||
#define APBDEV_PMC_IO_DPD2_REQ 0x1C0
|
||||
|
|
@ -51,9 +53,11 @@
|
|||
#define APBDEV_PMC_REG_SHORT 0x2CC
|
||||
#define APBDEV_PMC_SEC_DISABLE3 0x2D8
|
||||
#define APBDEV_PMC_SECURE_SCRATCH21 0x334
|
||||
#define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT 0x10
|
||||
#define APBDEV_PMC_SECURE_SCRATCH32 0x360
|
||||
#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
|
||||
#define APBDEV_PMC_CNTRL2 0x440
|
||||
#define PMC_CNTRL2_HOLD_CKE_LOW_EN 0x1000
|
||||
#define APBDEV_PMC_IO_DPD3_REQ 0x45C
|
||||
#define APBDEV_PMC_IO_DPD4_REQ 0x464
|
||||
#define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4
|
||||
|
|
|
|||
|
|
@ -88,7 +88,9 @@ intptr_t QueryIoMapping(u64 addr, u64 size);
|
|||
#define APB_MISC_PP_PINMUX_GLOBAL 0x40
|
||||
#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
|
||||
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
|
||||
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
|
||||
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
|
||||
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
|
||||
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
|
||||
#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue