exo2: Initial work on the exosphere rewrite.

exo2: Implement uncompressor stub and boot code up to Main(). exo2: implement some more init (uart/gic) exo2: implement more of init exo2: improve reg api, add keyslot flag setters exo2: implement se aes decryption/enc exo2: fix bugs in loader stub/mmu mappings exo2: start skeletoning bootconfig/global context types arch: fix makefile flags exo2: implement through master key derivation exo2: implement device master keygen exo2: more init through start of SetupSocSecurity exo2: implement pmc secure scratch management se: implement sticky bit validation libexosphere: fix building for arm32 libexo: fix makefile flags libexo: support building for arm64/arm sc7fw: skeleton binary sc7fw: skeleton a little more sc7fw: implement all non-dram functionality exo2: fix DivideUp error sc7fw: implement more dram code, fix reg library errors sc7fw: complete sc7fw impl. exo2: skeleton the rest of SetupSocSecurity exo2: implement fiq interrupt handler exo2: implement all exception handlers exo2: skeleton the entire smc api, implement the svc invoker exo2: implement rest of SetupSocSecurity exo2: correct slave security errors exo2: fix register definition exo2: minor fixes
2025-06-02 07:39:49 -04:00 · 2020-05-04 23:33:16 -07:00 · 2020-05-04 23:33:16 -07:00 · f66b41c027
commit f66b41c027
parent 71e0102f7a
192 changed files with 15093 additions and 24 deletions
--- a/libraries/libexosphere/include/exosphere.hpp
+++ b/libraries/libexosphere/include/exosphere.hpp
@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#include <exosphere/common.hpp>
+#include <exosphere/reg.hpp>
+#include <exosphere/hw.hpp>
+#include <exosphere/util.hpp>
+#include <exosphere/mmu.hpp>
+#include <exosphere/gic.hpp>
+#include <exosphere/wdt.hpp>
+#include <exosphere/pkg1.hpp>
+#include <exosphere/tsec.hpp>
+#include <exosphere/se.hpp>
+#include <exosphere/fuse.hpp>
+#include <exosphere/i2c.hpp>
+#include <exosphere/uart.hpp>
+#include <exosphere/pmic.hpp>
+#include <exosphere/log.hpp>
+#include <exosphere/clkrst.hpp>
+#include <exosphere/actmon.hpp>
+#include <exosphere/pmc.hpp>
+#include <exosphere/secmon.hpp>
+#include <exosphere/tegra.hpp>
--- a/libraries/libexosphere/include/exosphere/actmon.hpp
+++ b/libraries/libexosphere/include/exosphere/actmon.hpp
@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::actmon {
+
+    using InterruptHandler = void(*)();
+
+    void SetRegisterAddress(uintptr_t address);
+
+    void HandleInterrupt();
+
+    void StartMonitoringBpmp(InterruptHandler handler);
+    void StopMonitoringBpmp();
+
+}
--- a/libraries/libexosphere/include/exosphere/clkrst.hpp
+++ b/libraries/libexosphere/include/exosphere/clkrst.hpp
@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::clkrst {
+
+    void SetRegisterAddress(uintptr_t address);
+
+    void SetFuseVisibility(bool visible);
+
+    void EnableUartAClock();
+    void EnableUartBClock();
+    void EnableUartCClock();
+
+}
--- a/libraries/libexosphere/include/exosphere/common.hpp
+++ b/libraries/libexosphere/include/exosphere/common.hpp
@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#if 1 || defined(AMS_BUILD_FOR_AUDITING)
+#define EXOSPHERE_BUILD_FOR_AUDITING
+#endif
+
+#if defined(EXOSPHERE_BUILD_FOR_AUDITING) || defined(AMS_BUILD_FOR_DEBUGGING)
+#define EXOSPHERE_BUILD_FOR_DEBUGGING
+#endif
+
+#ifdef  EXOSPHERE_BUILD_FOR_DEBUGGING
+#define EXOSPHERE_ENABLE_ASSERTIONS
+#define EXOSPHERE_ENABLE_DEBUG_PRINT
+#endif
--- a/libraries/libexosphere/include/exosphere/fuse.hpp
+++ b/libraries/libexosphere/include/exosphere/fuse.hpp
@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/pmic.hpp>
+
+namespace ams::fuse {
+
+    enum HardwareType {
+        HardwareType_Icosa  = 0,
+        HardwareType_Copper = 1,
+        HardwareType_Hoag   = 2,
+        HardwareType_Iowa   = 3,
+        HardwareType_Calcio = 4,
+        HardwareType_Five   = 5,
+
+        HardwareType_Undefined = 0xF,
+    };
+
+    enum HardwareState {
+        HardwareState_Development = 0,
+        HardwareState_Production  = 1,
+        HardwareState_Undefined   = 2,
+    };
+
+    void SetRegisterAddress(uintptr_t address);
+    void SetWriteSecureOnly();
+    void Lockout();
+
+    u32 GetOdmWord(int index);
+
+    HardwareType    GetHardwareType();
+    HardwareState   GetHardwareState();
+    pmic::Regulator GetRegulator();
+
+}
--- a/libraries/libexosphere/include/exosphere/gic.hpp
+++ b/libraries/libexosphere/include/exosphere/gic.hpp
@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::gic {
+
+    enum InterruptMode {
+        InterruptMode_Level = 0,
+        InterruptMode_Edge  = 1,
+    };
+
+    constexpr inline s32 HighestPriority = 0;
+    constexpr inline s32 InterruptCount  = 224;
+
+    void SetRegisterAddress(uintptr_t distributor_address, uintptr_t cpu_interface_address);
+    void InitializeCommon();
+    void InitializeCoreUnique();
+
+    void SetPriority(int interrupt_id, int priority);
+    void SetInterruptGroup(int interrupt_id, int group);
+    void SetEnable(int interrupt_id, bool enable);
+    void SetSpiTargetCpu(int interrupt_id, u32 cpu_mask);
+    void SetSpiMode(int interrupt_id, InterruptMode mode);
+
+    int GetInterruptRequestId();
+    void SetEndOfInterrupt(int interrupt_id);
+
+}
--- a/libraries/libexosphere/include/exosphere/hw.hpp
+++ b/libraries/libexosphere/include/exosphere/hw.hpp
@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#if   defined(ATMOSPHERE_ARCH_ARM64)
+    #include <exosphere/hw/hw_arm64.hpp>
+    namespace ams::hw { using namespace ams::hw::arch::arm64; }
+#elif defined(ATMOSPHERE_ARCH_ARM)
+    #include <exosphere/hw/hw_arm.hpp>
+    namespace ams::hw { using namespace ams::hw::arch::arm; }
+#else
+    #error "Unknown architecture for hw!"
+#endif
--- a/libraries/libexosphere/include/exosphere/hw/hw_arm.hpp
+++ b/libraries/libexosphere/include/exosphere/hw/hw_arm.hpp
@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::hw::arch::arm {
+
+#ifdef __BPMP__
+    constexpr inline size_t DataCacheLineSize = 0x1;
+
+    ALWAYS_INLINE void DataSynchronizationBarrier() {
+        /* ... */
+    }
+
+    ALWAYS_INLINE void DataSynchronizationBarrierInnerShareable() {
+        /* ... */
+    }
+
+    ALWAYS_INLINE void DataMemoryBarrier() {
+        /* ... */
+    }
+
+    ALWAYS_INLINE void InstructionSynchronizationBarrier() {
+        /* ... */
+    }
+
+    ALWAYS_INLINE void FlushDataCache(const void *ptr, size_t size) {
+        AMS_UNUSED(ptr);
+        AMS_UNUSED(size);
+        /* ... */
+    }
+#else
+    #error "Unknown ARM board for ams::hw"
+#endif
+
+}
--- a/libraries/libexosphere/include/exosphere/hw/hw_arm64.hpp
+++ b/libraries/libexosphere/include/exosphere/hw/hw_arm64.hpp
@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/hw/hw_arm64_system_registers.hpp>
+#include <exosphere/hw/hw_arm64_cache.hpp>
+
+namespace ams::hw::arch::arm64 {
+
+    ALWAYS_INLINE void DataSynchronizationBarrier() {
+        __asm__ __volatile__("dsb sy" ::: "memory");
+    }
+
+    ALWAYS_INLINE void DataSynchronizationBarrierInnerShareable() {
+        __asm__ __volatile__("dsb ish" ::: "memory");
+    }
+
+    ALWAYS_INLINE void DataMemoryBarrier() {
+        __asm__ __volatile__("dmb sy" ::: "memory");
+    }
+
+    ALWAYS_INLINE void InstructionSynchronizationBarrier() {
+        __asm__ __volatile__("isb" ::: "memory");
+    }
+
+    ALWAYS_INLINE void WaitForInterrupt() {
+        __asm__ __volatile__("wfi" ::: "memory");
+    }
+
+    ALWAYS_INLINE void WaitForEvent() {
+        __asm__ __volatile__("wfe" ::: "memory");
+    }
+
+    ALWAYS_INLINE void SendEvent() {
+        __asm__ __volatile__("sev" ::: "memory");
+    }
+
+    ALWAYS_INLINE int CountLeadingZeros(u64 v) {
+        u64 z;
+        __asm__ __volatile__("clz %[z], %[v]" : [z]"=r"(z) : [v]"r"(v));
+        return z;
+    }
+
+    ALWAYS_INLINE int CountLeadingZeros(u32 v) {
+        u32 z;
+        __asm__ __volatile__("clz %w[z], %w[v]" : [z]"=r"(z) : [v]"r"(v));
+        return z;
+    }
+
+    ALWAYS_INLINE int GetCurrentCoreId() {
+        u64 mpidr;
+        HW_CPU_GET_MPIDR_EL1(mpidr);
+        return mpidr & 0xFF;
+    }
+
+}
--- a/libraries/libexosphere/include/exosphere/hw/hw_arm64_cache.hpp
+++ b/libraries/libexosphere/include/exosphere/hw/hw_arm64_cache.hpp
@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::hw::arch::arm64 {
+
+#if defined(ATMOSPHERE_CPU_ARM_CORTEX_A57) || defined(ATMOSPHERE_CPU_ARM_CORTEX_A53)
+    constexpr inline size_t InstructionCacheLineSize = 0x40;
+    constexpr inline size_t DataCacheLineSize        = 0x40;
+    constexpr inline size_t NumPerformanceCounters   = 6;
+#else
+    #error "Unknown CPU for cache line sizes"
+#endif
+
+    ALWAYS_INLINE void InvalidateEntireTlb() {
+        __asm__ __volatile__("tlbi alle3is" ::: "memory");
+    }
+
+    ALWAYS_INLINE void InvalidateDataCacheLine(void *ptr) {
+        __asm __volatile__("dc ivac, %[ptr]" :: [ptr]"r"(ptr) : "memory");
+    }
+
+    ALWAYS_INLINE void FlushDataCacheLine(void *ptr) {
+        __asm __volatile__("dc civac, %[ptr]" :: [ptr]"r"(ptr) : "memory");
+    }
+
+    ALWAYS_INLINE void InvalidateEntireInstructionCache() {
+        __asm__ __volatile__("ic iallu" ::: "memory");
+    }
+
+    ALWAYS_INLINE void InvalidateTlb(uintptr_t address) {
+        __asm__ __volatile__("tlbi vae3is, %[address]" :: [address]"r"(address) : "memory");
+    }
+
+    ALWAYS_INLINE void InvalidateTlbLastLevel(uintptr_t address) {
+        __asm__ __volatile__("tlbi vale3is, %[address]" :: [address]"r"(address) : "memory");
+    }
+
+    void FlushDataCache(const void *ptr, size_t size);
+
+}
--- a/libraries/libexosphere/include/exosphere/hw/hw_arm64_system_registers.hpp
+++ b/libraries/libexosphere/include/exosphere/hw/hw_arm64_system_registers.hpp
@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::hw::arch::arm64 {
+
+    #define HW_CPU_GET_SYSREG(name, value) __asm__ __volatile__("mrs %0, " #name "" : "=&r"(value) :: "memory");
+
+    #define HW_CPU_SET_SYSREG(name, value) __asm__ __volatile__("msr " #name ", %0" :: "r"(value) : "memory", "cc")
+
+    #define HW_CPU_GET_SCTLR_EL3(value) HW_CPU_GET_SYSREG(sctlr_el3, value)
+    #define HW_CPU_SET_SCTLR_EL3(value) HW_CPU_SET_SYSREG(sctlr_el3, value)
+
+    #define HW_CPU_GET_SCR_EL3(value) HW_CPU_GET_SYSREG(scr_el3, value)
+    #define HW_CPU_SET_SCR_EL3(value) HW_CPU_SET_SYSREG(scr_el3, value)
+
+    #define HW_CPU_GET_CPTR_EL3(value) HW_CPU_GET_SYSREG(cptr_el3, value)
+    #define HW_CPU_SET_CPTR_EL3(value) HW_CPU_SET_SYSREG(cptr_el3, value)
+
+    #define HW_CPU_GET_TTBR0_EL3(value) HW_CPU_GET_SYSREG(ttbr0_el3, value)
+    #define HW_CPU_SET_TTBR0_EL3(value) HW_CPU_SET_SYSREG(ttbr0_el3, value)
+
+    #define HW_CPU_GET_TCR_EL3(value) HW_CPU_GET_SYSREG(tcr_el3, value)
+    #define HW_CPU_SET_TCR_EL3(value) HW_CPU_SET_SYSREG(tcr_el3, value)
+
+    #define HW_CPU_GET_MAIR_EL3(value) HW_CPU_GET_SYSREG(mair_el3, value)
+    #define HW_CPU_SET_MAIR_EL3(value) HW_CPU_SET_SYSREG(mair_el3, value)
+
+    #define HW_CPU_GET_VBAR_EL3(value) HW_CPU_GET_SYSREG(vbar_el3, value)
+    #define HW_CPU_SET_VBAR_EL3(value) HW_CPU_SET_SYSREG(vbar_el3, value)
+
+    #define HW_CPU_GET_CLIDR_EL1(value) HW_CPU_GET_SYSREG(clidr_el1, value)
+    #define HW_CPU_SET_CLIDR_EL1(value) HW_CPU_SET_SYSREG(clidr_el1, value)
+
+    #define HW_CPU_GET_CCSIDR_EL1(value) HW_CPU_GET_SYSREG(ccsidr_el1, value)
+    #define HW_CPU_SET_CCSIDR_EL1(value) HW_CPU_SET_SYSREG(ccsidr_el1, value)
+
+    #define HW_CPU_GET_CSSELR_EL1(value) HW_CPU_GET_SYSREG(csselr_el1, value)
+    #define HW_CPU_SET_CSSELR_EL1(value) HW_CPU_SET_SYSREG(csselr_el1, value)
+
+    #define HW_CPU_GET_CPUACTLR_EL1(value) HW_CPU_GET_SYSREG(s3_1_c15_c2_0, value)
+    #define HW_CPU_SET_CPUACTLR_EL1(value) HW_CPU_SET_SYSREG(s3_1_c15_c2_0, value)
+
+    #define HW_CPU_GET_CPUECTLR_EL1(value) HW_CPU_GET_SYSREG(s3_1_c15_c2_1, value)
+    #define HW_CPU_SET_CPUECTLR_EL1(value) HW_CPU_SET_SYSREG(s3_1_c15_c2_1, value)
+
+    #define HW_CPU_GET_DBGAUTHSTATUS_EL1(value) HW_CPU_GET_SYSREG(dbgauthstatus_el1, value)
+    #define HW_CPU_SET_DBGAUTHSTATUS_EL1(value) HW_CPU_SET_SYSREG(dbgauthstatus_el1, value)
+
+    #define HW_CPU_GET_MPIDR_EL1(value) HW_CPU_GET_SYSREG(mpidr_el1, value)
+
+    #define HW_CPU_GET_OSLAR_EL1(value) HW_CPU_GET_SYSREG(oslar_el1, value)
+    #define HW_CPU_SET_OSLAR_EL1(value) HW_CPU_SET_SYSREG(oslar_el1, value)
+
+    #define HW_CPU_GET_OSDTRRX_EL1(value) HW_CPU_GET_SYSREG(osdtrrx_el1, value)
+    #define HW_CPU_SET_OSDTRRX_EL1(value) HW_CPU_SET_SYSREG(osdtrrx_el1, value)
+
+    #define HW_CPU_GET_OSDTRTX_EL1(value) HW_CPU_GET_SYSREG(osdtrtx_el1, value)
+    #define HW_CPU_SET_OSDTRTX_EL1(value) HW_CPU_SET_SYSREG(osdtrtx_el1, value)
+
+    #define HW_CPU_GET_MDSCR_EL1(value) HW_CPU_GET_SYSREG(mdscr_el1, value)
+    #define HW_CPU_SET_MDSCR_EL1(value) HW_CPU_SET_SYSREG(mdscr_el1, value)
+
+    #define HW_CPU_GET_OSECCR_EL1(value) HW_CPU_GET_SYSREG(oseccr_el1, value)
+    #define HW_CPU_SET_OSECCR_EL1(value) HW_CPU_SET_SYSREG(oseccr_el1, value)
+
+    #define HW_CPU_GET_MDCCINT_EL1(value) HW_CPU_GET_SYSREG(mdccint_el1, value)
+    #define HW_CPU_SET_MDCCINT_EL1(value) HW_CPU_SET_SYSREG(mdccint_el1, value)
+
+    #define HW_CPU_GET_DBGCLAIMCLR_EL1(value) HW_CPU_GET_SYSREG(dbgclaimclr_el1, value)
+    #define HW_CPU_SET_DBGCLAIMCLR_EL1(value) HW_CPU_SET_SYSREG(dbgclaimclr_el1, value)
+
+    #define HW_CPU_GET_DBGVCR32_EL2(value) HW_CPU_GET_SYSREG(dbgvcr32_el2, value)
+    #define HW_CPU_SET_DBGVCR32_EL2(value) HW_CPU_SET_SYSREG(dbgvcr32_el2, value)
+
+    #define HW_CPU_GET_SDER32_EL3(value) HW_CPU_GET_SYSREG(sder32_el3, value)
+    #define HW_CPU_SET_SDER32_EL3(value) HW_CPU_SET_SYSREG(sder32_el3, value)
+
+    #define HW_CPU_GET_MDCR_EL2(value) HW_CPU_GET_SYSREG(mdcr_el2, value)
+    #define HW_CPU_SET_MDCR_EL2(value) HW_CPU_SET_SYSREG(mdcr_el2, value)
+
+    #define HW_CPU_GET_MDCR_EL3(value) HW_CPU_GET_SYSREG(mdcr_el3, value)
+    #define HW_CPU_SET_MDCR_EL3(value) HW_CPU_SET_SYSREG(mdcr_el3, value)
+
+    #define HW_CPU_GET_SPSR_EL3(value) HW_CPU_GET_SYSREG(spsr_el3, value)
+    #define HW_CPU_SET_SPSR_EL3(value) HW_CPU_SET_SYSREG(spsr_el3, value)
+
+    #define HW_CPU_GET_DBGBVR0_EL1(value) HW_CPU_GET_SYSREG(dbgbvr0_el1, value)
+    #define HW_CPU_SET_DBGBVR0_EL1(value) HW_CPU_SET_SYSREG(dbgbvr0_el1, value)
+    #define HW_CPU_GET_DBGBCR0_EL1(value) HW_CPU_GET_SYSREG(dbgbcr0_el1, value)
+    #define HW_CPU_SET_DBGBCR0_EL1(value) HW_CPU_SET_SYSREG(dbgbcr0_el1, value)
+    #define HW_CPU_GET_DBGBVR1_EL1(value) HW_CPU_GET_SYSREG(dbgbvr1_el1, value)
+    #define HW_CPU_SET_DBGBVR1_EL1(value) HW_CPU_SET_SYSREG(dbgbvr1_el1, value)
+    #define HW_CPU_GET_DBGBCR1_EL1(value) HW_CPU_GET_SYSREG(dbgbcr1_el1, value)
+    #define HW_CPU_SET_DBGBCR1_EL1(value) HW_CPU_SET_SYSREG(dbgbcr1_el1, value)
+    #define HW_CPU_GET_DBGBVR2_EL1(value) HW_CPU_GET_SYSREG(dbgbvr2_el1, value)
+    #define HW_CPU_SET_DBGBVR2_EL1(value) HW_CPU_SET_SYSREG(dbgbvr2_el1, value)
+    #define HW_CPU_GET_DBGBCR2_EL1(value) HW_CPU_GET_SYSREG(dbgbcr2_el1, value)
+    #define HW_CPU_SET_DBGBCR2_EL1(value) HW_CPU_SET_SYSREG(dbgbcr2_el1, value)
+    #define HW_CPU_GET_DBGBVR3_EL1(value) HW_CPU_GET_SYSREG(dbgbvr3_el1, value)
+    #define HW_CPU_SET_DBGBVR3_EL1(value) HW_CPU_SET_SYSREG(dbgbvr3_el1, value)
+    #define HW_CPU_GET_DBGBCR3_EL1(value) HW_CPU_GET_SYSREG(dbgbcr3_el1, value)
+    #define HW_CPU_SET_DBGBCR3_EL1(value) HW_CPU_SET_SYSREG(dbgbcr3_el1, value)
+    #define HW_CPU_GET_DBGBVR4_EL1(value) HW_CPU_GET_SYSREG(dbgbvr4_el1, value)
+    #define HW_CPU_SET_DBGBVR4_EL1(value) HW_CPU_SET_SYSREG(dbgbvr4_el1, value)
+    #define HW_CPU_GET_DBGBCR4_EL1(value) HW_CPU_GET_SYSREG(dbgbcr4_el1, value)
+    #define HW_CPU_SET_DBGBCR4_EL1(value) HW_CPU_SET_SYSREG(dbgbcr4_el1, value)
+    #define HW_CPU_GET_DBGBVR5_EL1(value) HW_CPU_GET_SYSREG(dbgbvr5_el1, value)
+    #define HW_CPU_SET_DBGBVR5_EL1(value) HW_CPU_SET_SYSREG(dbgbvr5_el1, value)
+    #define HW_CPU_GET_DBGBCR5_EL1(value) HW_CPU_GET_SYSREG(dbgbcr5_el1, value)
+    #define HW_CPU_SET_DBGBCR5_EL1(value) HW_CPU_SET_SYSREG(dbgbcr5_el1, value)
+
+    #define HW_CPU_GET_DBGWVR0_EL1(value) HW_CPU_GET_SYSREG(dbgwvr0_el1, value)
+    #define HW_CPU_SET_DBGWVR0_EL1(value) HW_CPU_SET_SYSREG(dbgwvr0_el1, value)
+    #define HW_CPU_GET_DBGWCR0_EL1(value) HW_CPU_GET_SYSREG(dbgwcr0_el1, value)
+    #define HW_CPU_SET_DBGWCR0_EL1(value) HW_CPU_SET_SYSREG(dbgwcr0_el1, value)
+    #define HW_CPU_GET_DBGWVR1_EL1(value) HW_CPU_GET_SYSREG(dbgwvr1_el1, value)
+    #define HW_CPU_SET_DBGWVR1_EL1(value) HW_CPU_SET_SYSREG(dbgwvr1_el1, value)
+    #define HW_CPU_GET_DBGWCR1_EL1(value) HW_CPU_GET_SYSREG(dbgwcr1_el1, value)
+    #define HW_CPU_SET_DBGWCR1_EL1(value) HW_CPU_SET_SYSREG(dbgwcr1_el1, value)
+    #define HW_CPU_GET_DBGWVR2_EL1(value) HW_CPU_GET_SYSREG(dbgwvr2_el1, value)
+    #define HW_CPU_SET_DBGWVR2_EL1(value) HW_CPU_SET_SYSREG(dbgwvr2_el1, value)
+    #define HW_CPU_GET_DBGWCR2_EL1(value) HW_CPU_GET_SYSREG(dbgwcr2_el1, value)
+    #define HW_CPU_SET_DBGWCR2_EL1(value) HW_CPU_SET_SYSREG(dbgwcr2_el1, value)
+    #define HW_CPU_GET_DBGWVR3_EL1(value) HW_CPU_GET_SYSREG(dbgwvr3_el1, value)
+    #define HW_CPU_SET_DBGWVR3_EL1(value) HW_CPU_SET_SYSREG(dbgwvr3_el1, value)
+    #define HW_CPU_GET_DBGWCR3_EL1(value) HW_CPU_GET_SYSREG(dbgwcr3_el1, value)
+    #define HW_CPU_SET_DBGWCR3_EL1(value) HW_CPU_SET_SYSREG(dbgwcr3_el1, value)
+
+    /* https://developer.arm.com/docs/ddi0488/h/system-control/aarch64-register-descriptions/system-control-register-el3 */
+    struct SctlrEl3 {
+        using M   = util::BitPack32::Field< 0, 1>;
+        using A   = util::BitPack32::Field< 1, 1>;
+        using C   = util::BitPack32::Field< 2, 1>;
+        using Sa  = util::BitPack32::Field< 3, 1>;
+        using I   = util::BitPack32::Field<12, 1>;
+        using Wxn = util::BitPack32::Field<19, 1>;
+        using Ee  = util::BitPack32::Field<25, 1>;
+
+        static constexpr u32 Res1 = 0x30C50830;
+    };
+
+    /* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488c/BABGIHHJ.html */
+    struct ScrEl3 {
+        using Ns          = util::BitPack32::Field< 0, 1>;
+        using Irq         = util::BitPack32::Field< 1, 1>;
+        using Fiq         = util::BitPack32::Field< 2, 1>;
+        using Ea          = util::BitPack32::Field< 3, 1>;
+        using Fw          = util::BitPack32::Field< 4, 1>;
+        using Aw          = util::BitPack32::Field< 5, 1>;
+        using Net         = util::BitPack32::Field< 6, 1>;
+        using Smd         = util::BitPack32::Field< 7, 1>;
+        using Hce         = util::BitPack32::Field< 8, 1>;
+        using Sif         = util::BitPack32::Field< 9, 1>;
+        using RwCortexA53 = util::BitPack32::Field<10, 1>;
+        using StCortexA53 = util::BitPack32::Field<11, 1>;
+        using Twi         = util::BitPack32::Field<12, 1>;
+        using Twe         = util::BitPack32::Field<13, 1>;
+    };
+
+    /* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488c/CIHDEBIG.html */
+    struct CptrEl3 {
+        using Tfp   = util::BitPack32::Field<10, 1>;
+        using Tta   = util::BitPack32::Field<20, 1>;
+        using Tcpac = util::BitPack32::Field<31, 1>;
+    };
+
+    /* https://developer.arm.com/docs/ddi0488/h/system-control/aarch64-register-descriptions/translation-control-register-el3 */
+    struct TcrEl3 {
+        using T0sz  = util::BitPack32::Field< 0, 6>;
+        using Irgn0 = util::BitPack32::Field< 8, 2>;
+        using Orgn0 = util::BitPack32::Field<10, 2>;
+        using Sh0   = util::BitPack32::Field<12, 2>;
+        using Tg0   = util::BitPack32::Field<14, 2>;
+        using Ps    = util::BitPack32::Field<16, 3>;
+        using Tbi   = util::BitPack32::Field<20, 1>;
+
+        static constexpr u32 Res1 = 0x80800000;
+    };
+
+    struct ClidrEl1 {
+        using Ctype1 = util::BitPack32::Field< 0, 3>;
+        using Ctype2 = util::BitPack32::Field< 3, 3>;
+        using Ctype3 = util::BitPack32::Field< 6, 3>;
+        using Louis  = util::BitPack32::Field<21, 3>;
+        using Loc    = util::BitPack32::Field<24, 3>;
+        using Louu   = util::BitPack32::Field<27, 3>;
+    };
+
+    struct CcsidrEl1 {
+        using LineSize      = util::BitPack32::Field< 0,  3>;
+        using Associativity = util::BitPack32::Field< 3, 10>;
+        using NumSets       = util::BitPack32::Field<13, 15>;
+        using Wa            = util::BitPack32::Field<28,  1>;
+        using Ra            = util::BitPack32::Field<29,  1>;
+        using Wb            = util::BitPack32::Field<30,  1>;
+        using Wt            = util::BitPack32::Field<31,  1>;
+    };
+
+    struct CsselrEl1 {
+        using InD   = util::BitPack32::Field<0, 1>;
+        using Level = util::BitPack32::Field<1, 3>;
+    };
+
+    /* https://developer.arm.com/docs/ddi0488/h/system-control/aarch64-register-descriptions/cpu-auxiliary-control-register-el1 */
+    struct CpuactlrEl1CortexA57 {
+        /* TODO: Other bits */
+        using NonCacheableStreamingEnhancement                                          = util::BitPack64::Field<24, 1>;
+        /* TODO: Other bits */
+        using DisableLoadPassDmb                                                        = util::BitPack64::Field<59, 1>;
+        using ForceProcessorRcgEnablesActive                                            = util::BitPack64::Field<63, 1>;
+    };
+
+    /* https://developer.arm.com/docs/ddi0488/h/system-control/aarch64-register-descriptions/cpu-extended-control-register-el1 */
+    struct CpuectlrEl1CortexA57 {
+        using ProcessorDynamicRetentionControl         = util::BitPack64::Field< 0, 2>;
+        using Smpen                                    = util::BitPack64::Field< 6, 1>;
+        using L2LoadStoreDataPrefetchDistance          = util::BitPack64::Field<32, 2>;
+        using L2InstructionFetchPrefetchDistance       = util::BitPack64::Field<35, 2>;
+        using DisableTableWalkDescriptorAccessPrefetch = util::BitPack64::Field<38, 1>;
+    };
+
+    /* https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/dbgauthstatus_el1 */
+    struct DbgAuthStatusEl1 {
+        using Nsid  = util::BitPack32::Field<0, 2>;
+        using Nsnid = util::BitPack32::Field<2, 2>;
+        using Sid   = util::BitPack32::Field<4, 2>;
+        using Snid  = util::BitPack32::Field<6, 2>;
+    };
+
+}
--- a/libraries/libexosphere/include/exosphere/i2c.hpp
+++ b/libraries/libexosphere/include/exosphere/i2c.hpp
@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::i2c {
+
+    enum Port {
+        Port_1 = 0,
+        /* TODO: Support other ports? */
+        Port_5 = 4,
+
+        Port_Count = 5,
+    };
+
+    void SetRegisterAddress(Port port, uintptr_t address);
+
+    void Initialize(Port port);
+
+    bool Query(void *dst, size_t dst_size, Port port, int address, int r);
+    bool Send(Port port, int address, int r, const void *src, size_t src_size);
+
+    inline u8 QueryByte(Port port, int address, int r) {
+        u8 byte;
+        Query(std::addressof(byte), sizeof(byte), port, address, r);
+        return byte;
+    }
+
+    inline void SendByte(Port port, int address, int r, u8 byte) {
+        Send(port, address, r, std::addressof(byte), sizeof(byte));
+    }
+
+}
--- a/libraries/libexosphere/include/exosphere/log.hpp
+++ b/libraries/libexosphere/include/exosphere/log.hpp
@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::log {
+
+    void Initialize();
+
+}
--- a/libraries/libexosphere/include/exosphere/mmu.hpp
+++ b/libraries/libexosphere/include/exosphere/mmu.hpp
@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/mmu/mmu_api.hpp>
--- a/libraries/libexosphere/include/exosphere/mmu/mmu_api.arch.arm.hpp
+++ b/libraries/libexosphere/include/exosphere/mmu/mmu_api.arch.arm.hpp
@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::mmu::arch::arm {
+
+    /* NOTE: mmu is not supported by libexosphere-on-arm. */
+    /* However, we want the memory layout to be parseable, so we will include some arm64 mmu definitions. */
+    constexpr inline u64 L1EntryShift = 30;
+    constexpr inline u64 L2EntryShift = 21;
+    constexpr inline u64 L3EntryShift = 12;
+
+    constexpr inline u64 L1EntrySize = 1_GB;
+    constexpr inline u64 L2EntrySize = 2_MB;
+    constexpr inline u64 L3EntrySize = 4_KB;
+
+    constexpr inline u64 PageSize = L3EntrySize;
+
+    constexpr inline u64 L1EntryMask = ((static_cast<u64>(1) << (48 - L1EntryShift)) - 1) << L1EntryShift;
+    constexpr inline u64 L2EntryMask = ((static_cast<u64>(1) << (48 - L2EntryShift)) - 1) << L2EntryShift;
+    constexpr inline u64 L3EntryMask = ((static_cast<u64>(1) << (48 - L3EntryShift)) - 1) << L3EntryShift;
+
+    constexpr inline u64 TableEntryMask = L3EntryMask;
+
+    static_assert(L1EntryMask == 0x0000FFFFC0000000ul);
+    static_assert(L2EntryMask == 0x0000FFFFFFE00000ul);
+    static_assert(L3EntryMask == 0x0000FFFFFFFFF000ul);
+
+}
--- a/libraries/libexosphere/include/exosphere/mmu/mmu_api.arch.arm64.hpp
+++ b/libraries/libexosphere/include/exosphere/mmu/mmu_api.arch.arm64.hpp
@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::mmu::arch::arm64 {
+
+    enum PageTableTableAttribute : u64 {
+        PageTableTableAttribute_None                   = (0ul <<  0),
+        PageTableTableAttribute_PrivilegedExecuteNever = (1ul << 59),
+        PageTableTableAttribute_ExecuteNever           = (1ul << 60),
+        PageTableTableAttribute_NonSecure              = (1ul << 63),
+
+        PageTableTableAttributes_El3SecureCode          = PageTableTableAttribute_None,
+        PageTableTableAttributes_El3SecureData          = PageTableTableAttribute_ExecuteNever,
+        PageTableTableAttributes_El3NonSecureCode       = PageTableTableAttributes_El3SecureCode | PageTableTableAttribute_NonSecure,
+        PageTableTableAttributes_El3NonSecureData       = PageTableTableAttributes_El3SecureData | PageTableTableAttribute_NonSecure,
+    };
+
+    enum PageTableMappingAttribute : u64{
+        /* Security. */
+        PageTableMappingAttribute_NonSecure = (1ul << 5),
+
+        /* El1 Access. */
+        PageTableMappingAttribute_El1NotAllowed = (0ul << 6),
+        PageTableMappingAttribute_El1Allowed    = (1ul << 6),
+
+        /* RW Permission. */
+        PageTableMappingAttribute_PermissionReadWrite = (0ul << 7),
+        PageTableMappingAttribute_PermissionReadOnly  = (1ul << 7),
+
+        /* Shareability. */
+        PageTableMappingAttribute_ShareabilityNonShareable   = (0ul << 8),
+        PageTableMappingAttribute_ShareabiltiyOuterShareable = (2ul << 8),
+        PageTableMappingAttribute_ShareabilityInnerShareable = (3ul << 8),
+
+        /* Access flag. */
+        PageTableMappingAttribute_AccessFlagNotAccessed = (0ul << 10),
+        PageTableMappingAttribute_AccessFlagAccessed    = (1ul << 10),
+
+        /* Global. */
+        PageTableMappingAttribute_Global    = (0ul << 11),
+        PageTableMappingAttribute_NonGlobal = (1ul << 11),
+
+        /* Contiguous */
+        PageTableMappingAttribute_NonContiguous          = (0ul << 52),
+        PageTableMappingAttribute_Contiguous             = (1ul << 52),
+
+        /* Privileged Execute Never */
+        PageTableMappingAttribute_PrivilegedExecuteNever = (1ul << 53),
+
+        /* Execute Never */
+        PageTableMappingAttribute_ExecuteNever = (1ul << 54),
+
+
+        /* Useful definitions. */
+        PageTableMappingAttributes_El3SecureRwCode = (
+            PageTableMappingAttribute_PermissionReadWrite       |
+            PageTableMappingAttribute_ShareabilityInnerShareable
+        ),
+
+        PageTableMappingAttributes_El3SecureRoCode = (
+            PageTableMappingAttribute_PermissionReadOnly        |
+            PageTableMappingAttribute_ShareabilityInnerShareable
+        ),
+
+        PageTableMappingAttributes_El3SecureRoData = (
+            PageTableMappingAttribute_PermissionReadOnly         |
+            PageTableMappingAttribute_ShareabilityInnerShareable |
+            PageTableMappingAttribute_ExecuteNever
+        ),
+
+        PageTableMappingAttributes_El3SecureRwData = (
+            PageTableMappingAttribute_PermissionReadWrite        |
+            PageTableMappingAttribute_ShareabilityInnerShareable |
+            PageTableMappingAttribute_ExecuteNever
+        ),
+
+        PageTableMappingAttributes_El3NonSecureRwCode = PageTableMappingAttributes_El3SecureRwCode | PageTableMappingAttribute_NonSecure,
+        PageTableMappingAttributes_El3NonSecureRoCode = PageTableMappingAttributes_El3SecureRoCode | PageTableMappingAttribute_NonSecure,
+        PageTableMappingAttributes_El3NonSecureRoData = PageTableMappingAttributes_El3SecureRoData | PageTableMappingAttribute_NonSecure,
+        PageTableMappingAttributes_El3NonSecureRwData = PageTableMappingAttributes_El3SecureRwData | PageTableMappingAttribute_NonSecure,
+
+
+        PageTableMappingAttributes_El3SecureDevice    = PageTableMappingAttributes_El3SecureRwData,
+        PageTableMappingAttributes_El3NonSecureDevice = PageTableMappingAttributes_El3NonSecureRwData,
+    };
+
+    enum MemoryRegionAttribute : u64 {
+        MemoryRegionAttribute_Device_nGnRnE            = (0ul << 2),
+        MemoryRegionAttribute_Device_nGnRE             = (1ul << 2),
+        MemoryRegionAttribute_NormalMemory             = (2ul << 2),
+        MemoryRegionAttribute_NormalMemoryNotCacheable = (3ul << 2),
+
+        MemoryRegionAttribute_NormalInnerShift = 0,
+        MemoryRegionAttribute_NormalOuterShift = 4,
+
+        #define AMS_MRA_DEFINE_NORMAL_ATTR(__NAME__, __VAL__)                                                  \
+            MemoryRegionAttribute_NormalInner##__NAME__ = (__VAL__ << MemoryRegionAttribute_NormalInnerShift), \
+            MemoryRegionAttribute_NormalOuter##__NAME__ = (__VAL__ << MemoryRegionAttribute_NormalOuterShift)
+
+        AMS_MRA_DEFINE_NORMAL_ATTR(NonCacheable, 4),
+
+        AMS_MRA_DEFINE_NORMAL_ATTR(WriteAllocate, (1ul << 0)),
+        AMS_MRA_DEFINE_NORMAL_ATTR(ReadAllocate,  (1ul << 1)),
+
+        AMS_MRA_DEFINE_NORMAL_ATTR(WriteThroughTransient,    (0ul << 2)),
+        AMS_MRA_DEFINE_NORMAL_ATTR(WriteBackTransient,       (1ul << 2)),
+        AMS_MRA_DEFINE_NORMAL_ATTR(WriteThroughNonTransient, (2ul << 2)),
+        AMS_MRA_DEFINE_NORMAL_ATTR(WriteBackNonTransient,    (3ul << 2)),
+
+        #undef AMS_MRA_DEFINE_NORMAL_ATTR
+
+        MemoryRegionAttributes_Normal = (
+            MemoryRegionAttribute_NormalInnerReadAllocate          |
+            MemoryRegionAttribute_NormalOuterReadAllocate          |
+            MemoryRegionAttribute_NormalInnerWriteAllocate         |
+            MemoryRegionAttribute_NormalOuterWriteAllocate         |
+            MemoryRegionAttribute_NormalInnerWriteBackNonTransient |
+            MemoryRegionAttribute_NormalOuterWriteBackNonTransient
+        ),
+
+        MemoryRegionAttributes_Device = (
+            MemoryRegionAttribute_Device_nGnRE
+        ),
+    };
+
+    constexpr inline u64 MemoryRegionAttributeWidth = 8;
+
+    constexpr PageTableMappingAttribute AddMappingAttributeIndex(PageTableMappingAttribute attr, int index) {
+        return static_cast<PageTableMappingAttribute>(attr | (static_cast<typename std::underlying_type<PageTableMappingAttribute>::type>(index) << 2));
+    }
+
+    constexpr inline u64 L1EntryShift = 30;
+    constexpr inline u64 L2EntryShift = 21;
+    constexpr inline u64 L3EntryShift = 12;
+
+    constexpr inline u64 L1EntrySize = 1_GB;
+    constexpr inline u64 L2EntrySize = 2_MB;
+    constexpr inline u64 L3EntrySize = 4_KB;
+
+    constexpr inline u64 PageSize = L3EntrySize;
+
+    constexpr inline u64 L1EntryMask = ((1ul << (48 - L1EntryShift)) - 1) << L1EntryShift;
+    constexpr inline u64 L2EntryMask = ((1ul << (48 - L2EntryShift)) - 1) << L2EntryShift;
+    constexpr inline u64 L3EntryMask = ((1ul << (48 - L3EntryShift)) - 1) << L3EntryShift;
+
+    constexpr inline u64 TableEntryMask = L3EntryMask;
+
+    static_assert(L1EntryMask == 0x0000FFFFC0000000ul);
+    static_assert(L2EntryMask == 0x0000FFFFFFE00000ul);
+    static_assert(L3EntryMask == 0x0000FFFFFFFFF000ul);
+
+    constexpr inline u64 TableEntryIndexMask = 0x1FF;
+
+    constexpr inline u64 EntryBlock = 0x1ul;
+    constexpr inline u64 EntryPage  = 0x3ul;
+
+    constexpr u64 MakeTableEntry(u64 address, PageTableTableAttribute attr) {
+        return address | static_cast<u64>(attr) | 0x3ul;
+    }
+
+    constexpr u64 MakeL1BlockEntry(u64 address, PageTableMappingAttribute attr) {
+        return address | static_cast<u64>(attr) | 0x1ul;
+    }
+
+    constexpr u64 MakeL2BlockEntry(u64 address, PageTableMappingAttribute attr) {
+        return address | static_cast<u64>(attr) | 0x1ul;
+    }
+
+    constexpr u64 MakeL3BlockEntry(u64 address, PageTableMappingAttribute attr) {
+        return address | static_cast<u64>(attr) | 0x3ul;
+    }
+
+    constexpr uintptr_t GetL2Offset(uintptr_t address) {
+        return address & ((1ul << L2EntryShift) - 1);
+    }
+
+    constexpr u64 GetL1EntryIndex(uintptr_t address) {
+        return ((address >> L1EntryShift) & TableEntryIndexMask);
+    }
+
+    constexpr u64 GetL2EntryIndex(uintptr_t address) {
+        return ((address >> L2EntryShift) & TableEntryIndexMask);
+    }
+
+    constexpr u64 GetL3EntryIndex(uintptr_t address) {
+        return ((address >> L3EntryShift) & TableEntryIndexMask);
+    }
+
+    constexpr ALWAYS_INLINE void SetTableImpl(u64 *table, u64 index, u64 value) {
+        /* Ensure (for constexpr validation purposes) that the entry we set is clear. */
+        if (table[index]) {
+            __builtin_unreachable();
+        }
+
+        /* Set the value. */
+        table[index] = value;
+    }
+
+    constexpr void SetL1TableEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, PageTableTableAttribute attr) {
+        SetTableImpl(table, GetL1EntryIndex(virt_addr), MakeTableEntry(phys_addr & TableEntryMask, attr));
+    }
+
+    constexpr void SetL2TableEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, PageTableTableAttribute attr) {
+        SetTableImpl(table, GetL2EntryIndex(virt_addr), MakeTableEntry(phys_addr & TableEntryMask, attr));
+    }
+
+    constexpr void SetL1BlockEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, size_t size, PageTableMappingAttribute attr) {
+        const u64 start = GetL1EntryIndex(virt_addr);
+        const u64 count = (size >> L1EntryShift);
+
+        for (u64 i = 0; i < count; ++i) {
+            SetTableImpl(table, start + i, MakeL1BlockEntry((phys_addr & L1EntryMask) + (i << L1EntryShift), attr));
+        }
+    }
+
+    constexpr void SetL2BlockEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, size_t size, PageTableMappingAttribute attr) {
+        const u64 start = GetL2EntryIndex(virt_addr);
+        const u64 count = (size >> L2EntryShift);
+
+        for (u64 i = 0; i < count; ++i) {
+            SetTableImpl(table, start + i, MakeL2BlockEntry((phys_addr & L2EntryMask) + (i << L2EntryShift), attr));
+        }
+    }
+
+    constexpr void SetL3BlockEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, size_t size, PageTableMappingAttribute attr) {
+        const u64 start = GetL3EntryIndex(virt_addr);
+        const u64 count = (size >> L3EntryShift);
+
+        for (u64 i = 0; i < count; ++i) {
+            SetTableImpl(table, start + i, MakeL3BlockEntry((phys_addr & L3EntryMask) + (i << L3EntryShift), attr));
+        }
+    }
+
+    constexpr void InvalidateL1Entries(u64 *table, uintptr_t virt_addr, size_t size) {
+        const u64 start = GetL1EntryIndex(virt_addr);
+        const u64 count = (size >> L1EntryShift);
+        const u64 end   = start + count;
+
+        for (u64 i = start; i < end; ++i) {
+            table[i] = 0;
+        }
+    }
+
+    constexpr void InvalidateL2Entries(u64 *table, uintptr_t virt_addr, size_t size) {
+        const u64 start = GetL2EntryIndex(virt_addr);
+        const u64 count = (size >> L2EntryShift);
+        const u64 end   = start + count;
+
+        for (u64 i = start; i < end; ++i) {
+            table[i] = 0;
+        }
+    }
+
+    constexpr void InvalidateL3Entries(u64 *table, uintptr_t virt_addr, size_t size) {
+        const u64 start = GetL3EntryIndex(virt_addr);
+        const u64 count = (size >> L3EntryShift);
+        const u64 end   = start + count;
+
+        for (u64 i = start; i < end; ++i) {
+            table[i] = 0;
+        }
+    }
+
+}
--- a/libraries/libexosphere/include/exosphere/mmu/mmu_api.hpp
+++ b/libraries/libexosphere/include/exosphere/mmu/mmu_api.hpp
@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#if defined(ATMOSPHERE_ARCH_ARM64)
+    #include <exosphere/mmu/mmu_api.arch.arm64.hpp>
+#elif defined(ATMOSPHERE_ARCH_ARM)
+    #include <exosphere/mmu/mmu_api.arch.arm.hpp>
+#else
+    #error "Unknown architecture for mmu!"
+#endif
+
+namespace ams::mmu {
+
+    #if defined(ATMOSPHERE_ARCH_ARM64)
+        using namespace ams::mmu::arch::arm64;
+    #elif defined(ATMOSPHERE_ARCH_ARM)
+        using namespace ams::mmu::arch::arm;
+    #else
+        #error "Unknown architecture for mmu!"
+    #endif
+
+}
--- a/libraries/libexosphere/include/exosphere/pkg1.hpp
+++ b/libraries/libexosphere/include/exosphere/pkg1.hpp
@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/pkg1/pkg1_bootloader_parameters.hpp>
+#include <exosphere/pkg1/pkg1_boot_config.hpp>
+#include <exosphere/pkg1/pkg1_error_types.hpp>
+#include <exosphere/pkg1/pkg1_key_generation.hpp>
+#include <exosphere/pkg1/pkg1_se_key_slots.hpp>
--- a/libraries/libexosphere/include/exosphere/pkg1/pkg1_boot_config.hpp
+++ b/libraries/libexosphere/include/exosphere/pkg1/pkg1_boot_config.hpp
@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::pkg1 {
+
+    enum MemorySize {
+        MemorySize_4GB = 0,
+        MemorySize_6GB = 1,
+        MemorySize_8GB = 2,
+    };
+
+    enum MemoryArrange {
+        MemoryArrange_Normal    = 1,
+        MemoryArrange_AppletDev = 2,
+        MemoryArrange_SystemDev = 2,
+    };
+
+    enum MemoryMode {
+        MemoryMode_SizeShift = 4,
+        MemoryMode_SizeMask  = 0x30,
+
+        MemoryMode_ArrangeMask = 0x0F,
+
+        MemoryMode_Auto = 0x00,
+
+        MemoryMode_4GB          = ((MemorySize_4GB << MemoryMode_SizeShift) | (MemoryArrange_Normal)),
+        MemoryMode_4GBAppletDev = ((MemorySize_4GB << MemoryMode_SizeShift) | (MemoryArrange_AppletDev)),
+        MemoryMode_4GBSystemDev = ((MemorySize_4GB << MemoryMode_SizeShift) | (MemoryArrange_SystemDev)),
+
+        MemoryMode_6GB          = ((MemorySize_6GB << MemoryMode_SizeShift) | (MemoryArrange_Normal)),
+        MemoryMode_6GBAppletDev = ((MemorySize_6GB << MemoryMode_SizeShift) | (MemoryArrange_AppletDev)),
+
+        MemoryMode_8GB          = ((MemorySize_8GB << MemoryMode_SizeShift) | (MemoryArrange_Normal)),
+    };
+
+    constexpr ALWAYS_INLINE MemorySize GetMemorySize(MemoryMode mode) {
+        return static_cast<MemorySize>(mode >> MemoryMode_SizeShift);
+    }
+
+    constexpr ALWAYS_INLINE MemoryArrange GetMemoryArrange(MemoryMode mode) {
+        return static_cast<MemoryArrange>(mode & MemoryMode_ArrangeMask);
+    }
+
+    constexpr ALWAYS_INLINE MemoryMode MakeMemoryMode(MemorySize size, MemoryArrange arrange) {
+        return static_cast<MemoryMode>((size << MemoryMode_SizeShift) | (arrange));
+    }
+
+    struct BootConfigData {
+        u32 version;
+        u32 reserved_04;
+        u32 reserved_08;
+        u32 reserved_0C;
+        u8 flags1[0x10];
+        u8 flags0[0x10];
+        u64 initial_tsc_value;
+        u8 padding_38[0x200 - 0x38];
+
+        constexpr bool IsDevelopmentFunctionEnabled() const {
+            return (this->flags1[0] & (1 << 1)) != 0;
+        }
+
+        constexpr bool IsSErrorDebugEnabled() const {
+            return (this->flags1[0] & (1 << 2)) != 0;
+        }
+
+        constexpr u8 GetKernelFlags0() const {
+            return this->flags0[1];
+        }
+
+        constexpr u8 GetKernelFlags1() const {
+            return this->flags1[0];
+        }
+
+        constexpr MemoryMode GetMemoryMode() const {
+            return static_cast<MemoryMode>(this->flags0[3]);
+        }
+
+        bool IsTscInitialValueValid() const {
+            return (this->flags0[4] & (1 << 0)) != 0;
+        }
+    };
+    static_assert(util::is_pod<BootConfigData>::value);
+    static_assert(sizeof(BootConfigData) == 0x200);
+
+    struct BootConfigSignedData {
+        u32 version;
+        u32 reserved_04;
+        u8  flags;
+        u8  reserved_09[0x10 - 9];
+        u8  ecid[0x10];
+        u8  flags1[0x10];
+        u8  flags0[0x10];
+        u8  padding_40[0x100 - 0x40];
+
+        constexpr bool IsPackage2EncryptionDisabled() const {
+            return (this->flags & (1 << 0)) != 0;
+        }
+
+        constexpr bool IsPackage2SignatureVerificationDisabled() const {
+            return (this->flags & (1 << 1)) != 0;
+        }
+
+        constexpr bool IsProgramVerificationDisabled() const {
+            return (this->flags1[0] & (1 << 0)) != 0;
+        }
+    };
+    static_assert(util::is_pod<BootConfigSignedData>::value);
+    static_assert(sizeof(BootConfigSignedData) == 0x100);
+
+    struct BootConfig {
+        BootConfigData data;
+        u8 signature[0x100];
+        BootConfigSignedData signed_data;
+    };
+    static_assert(util::is_pod<BootConfig>::value);
+    static_assert(sizeof(BootConfig) == 0x400);
+
+}
--- a/libraries/libexosphere/include/exosphere/pkg1/pkg1_bootloader_parameters.hpp
+++ b/libraries/libexosphere/include/exosphere/pkg1/pkg1_bootloader_parameters.hpp
@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::pkg1 {
+
+    enum BootloaderState {
+        BootloaderState_Start            = 0,
+        BootloaderState_LoadedBootConfig = 1,
+        BootloaderState_InitializedDram  = 2,
+        BootloaderState_LoadedPackage2   = 3,
+        BootloaderState_Done             = 4,
+    };
+
+    enum SecureMonitorState {
+        SecureMonitorState_Start       = 0,
+        SecureMonitorState_Initialized = 1,
+    };
+
+    struct BctParameters {
+        u32 bootloader_version;
+        u32 bootloader_start_block;
+        u32 bootloader_start_page;
+        u32 bootloader_attributes;
+    };
+    static_assert(util::is_pod<BctParameters>::value && sizeof(BctParameters) == 0x10);
+
+    struct SecureMonitorParameters {
+        u32 bootloader_start_time;
+        u32 bootloader_end_time;
+        u32 secmon_start_time;
+        u32 secmon_end_time;
+        BctParameters bct_params;
+        u8 reserved[0xD8];
+        u32 bootloader_state;
+        u32 secmon_state;
+        u8 reserved2[0x100];
+    };
+    static_assert(util::is_pod<SecureMonitorParameters>::value);
+    static_assert(sizeof(SecureMonitorParameters) == 0x200);
+
+    static_assert(offsetof(SecureMonitorParameters, bct_params)       == 0x10);
+    static_assert(offsetof(SecureMonitorParameters, bootloader_state) == 0xF8);
+    static_assert(offsetof(SecureMonitorParameters, secmon_state) == 0xFC);
+
+    enum BootloaderAttribute {
+        BootloaderAttribute_None         = (0u << 0),
+        BootloaderAttribute_RecoveryBoot = (1u << 0),
+
+        BootloaderAttribute_RestrictedSmcShift = 1,
+        BootloaderAttribute_RestrictedSmcMask  = (0xFu << BootloaderAttribute_RestrictedSmcShift),
+    };
+
+}
--- a/libraries/libexosphere/include/exosphere/pkg1/pkg1_error_types.hpp
+++ b/libraries/libexosphere/include/exosphere/pkg1/pkg1_error_types.hpp
@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::pkg1 {
+
+    enum ErrorReason {
+        ErrorReason_None                            = 0,
+        ErrorReason_InvalidPackage2Signature        = 1,
+        ErrorReason_InvalidPackage2Meta             = 2,
+        ErrorReason_InvalidPackage2Version          = 3,
+        ErrorReason_InvalidPackage2Payload          = 4,
+        ErrorReason_UnknownSmc                      = 5,
+        ErrorReason_UnknownAbort                    = 6,
+        ErrorReason_InvalidCoreContext              = 7,
+        ErrorReason_InvalidSecurityEngineStickyBits = 8,
+        ErrorReason_UnexpectedReset                 = 9,
+
+        ErrorReason_Exception                       = 0x10,
+
+        ErrorReason_TransitionToSafeMode            = 0x20,
+        ErrorReason_SecureInitializerReboot         = 0x21,
+
+        ErrorReason_SdmmcError                      = 0x30,
+        ErrorReason_InvalidDramId                   = 0x31,
+        ErrorReason_InvalidPackage2                 = 0x32,
+        ErrorReason_InvalidBct                      = 0x33,
+        ErrorReason_InvalidGpt                      = 0x34,
+        ErrorReason_FailedToTransitionToSafeMode    = 0x35,
+        ErrorReason_ActivityMonitorInterrupt        = 0x36,
+
+        ErrorReason_KernelPanic                     = 0x40,
+    };
+
+    enum ErrorColor {
+        ErrorColor_Black     = 0x000,
+
+        ErrorColor_Red       = 0x00F,
+        ErrorColor_Yellow    = 0x0FF,
+        ErrorColor_Orange    = 0x07F,
+        ErrorColor_Blue      = 0xF00,
+        ErrorColor_LightBlue = 0xFF0,
+        ErrorColor_Pink      = 0xF7F,
+        ErrorColor_Purple    = 0xF0A,
+    };
+
+    enum ErrorInfo {
+        ErrorInfo_ReasonMask = 0xFF,
+        ErrorInfo_ColorShift = 20,
+
+        #define MAKE_ERROR_INFO(_COLOR_, _DESC_) ((static_cast<u32>(ErrorColor_##_COLOR_) << ErrorInfo_ColorShift) | (ErrorReason_##_DESC_))
+
+        ErrorInfo_None                            = MAKE_ERROR_INFO(Black,     None),
+
+        ErrorInfo_InvalidPackage2Signature        = MAKE_ERROR_INFO(Blue,      InvalidPackage2Signature),
+        ErrorInfo_InvalidPackage2Meta             = MAKE_ERROR_INFO(Blue,      InvalidPackage2Meta),
+        ErrorInfo_InvalidPackage2Version          = MAKE_ERROR_INFO(Blue,      InvalidPackage2Version),
+        ErrorInfo_InvalidPackage2Payload          = MAKE_ERROR_INFO(Blue,      InvalidPackage2Payload),
+
+        ErrorInfo_UnknownSmc                      = MAKE_ERROR_INFO(LightBlue, UnknownSmc),
+
+        ErrorInfo_UnknownAbort                    = MAKE_ERROR_INFO(Yellow,    UnknownAbort),
+
+        ErrorInfo_InvalidCoreContext              = MAKE_ERROR_INFO(Pink,      InvalidCoreContext),
+        ErrorInfo_InvalidSecurityEngineStickyBits = MAKE_ERROR_INFO(Pink,      InvalidSecurityEngineStickyBits),
+        ErrorInfo_UnexpectedReset                 = MAKE_ERROR_INFO(Pink,      UnexpectedReset),
+
+        ErrorInfo_Exception                       = MAKE_ERROR_INFO(Orange,    Exception),
+
+        ErrorInfo_TransitionToSafeMode            = MAKE_ERROR_INFO(Black,     TransitionToSafeMode),
+        ErrorInfo_SecureInitializerReboot         = MAKE_ERROR_INFO(Black,     SecureInitializerReboot),
+
+        ErrorInfo_SdmmcError                      = MAKE_ERROR_INFO(Purple,    SdmmcError),
+        ErrorInfo_InvalidDramId                   = MAKE_ERROR_INFO(Purple,    InvalidDramId),
+        ErrorInfo_InvalidPackage2                 = MAKE_ERROR_INFO(Purple,    InvalidPackage2),
+        ErrorInfo_InvalidBct                      = MAKE_ERROR_INFO(Purple,    InvalidBct),
+        ErrorInfo_InvalidGpt                      = MAKE_ERROR_INFO(Purple,    InvalidGpt),
+        ErrorInfo_FailedToTransitionToSafeMode    = MAKE_ERROR_INFO(Purple,    FailedToTransitionToSafeMode),
+        ErrorInfo_ActivityMonitorInterrupt        = MAKE_ERROR_INFO(Purple,    ActivityMonitorInterrupt),
+
+        #undef MAKE_ERROR_INFO
+    };
+
+    constexpr inline ErrorReason GetErrorReason(u32 info) {
+        return static_cast<ErrorReason>(info & ErrorInfo_ReasonMask);
+    }
+
+    constexpr inline ErrorInfo MakeKernelPanicResetInfo(u32 color) {
+        return static_cast<ErrorInfo>((color << ErrorInfo_ColorShift) | (ErrorReason_KernelPanic));
+    }
+
+    #define PKG1_SECURE_MONITOR_PMC_ERROR_SCRATCH (0x840)
+
+}
--- a/libraries/libexosphere/include/exosphere/pkg1/pkg1_key_generation.hpp
+++ b/libraries/libexosphere/include/exosphere/pkg1/pkg1_key_generation.hpp
@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::pkg1 {
+
+    enum KeyGeneration : int {
+
+        KeyGeneration_1_0_0 = 0x00,
+        KeyGeneration_3_0_0 = 0x01,
+        KeyGeneration_3_0_1 = 0x02,
+        KeyGeneration_4_0_0 = 0x03,
+        KeyGeneration_5_0_0 = 0x04,
+        KeyGeneration_6_0_0 = 0x05,
+        KeyGeneration_6_2_0 = 0x06,
+        KeyGeneration_7_0_0 = 0x07,
+        KeyGeneration_8_1_0 = 0x08,
+        KeyGeneration_9_0_0 = 0x09,
+        KeyGeneration_9_1_0 = 0x0A,
+
+        KeyGeneration_Count,
+
+        KeyGeneration_Current = KeyGeneration_Count - 1,
+
+        KeyGeneration_Min = 0x00,
+        KeyGeneration_Max = 0x20,
+    };
+    static_assert(KeyGeneration_Count <= KeyGeneration_Max);
+
+    constexpr inline const int OldMasterKeyCount       = KeyGeneration_Count - 1;
+    constexpr inline const int OldDeviceMasterKeyCount = KeyGeneration_Count - KeyGeneration_4_0_0;
+
+}
--- a/libraries/libexosphere/include/exosphere/pkg1/pkg1_se_key_slots.hpp
+++ b/libraries/libexosphere/include/exosphere/pkg1/pkg1_se_key_slots.hpp
@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::pkg1 {
+
+    enum AesKeySlot {
+        AesKeySlot_UserStart                = 0,
+
+        AesKeySlot_TzramSave                = 2,
+
+        AesKeySlot_UserLast                 = 5,
+        AesKeySlot_UserEnd                  = AesKeySlot_UserLast + 1,
+
+        AesKeySlot_SecmonStart              = 8,
+
+        AesKeySlot_Temporary                =  8,
+        AesKeySlot_Smc                      =  9,
+        AesKeySlot_RandomForUserWrap        = 10,
+        AesKeySlot_RandomForKeyStorageWrap  = 11,
+        AesKeySlot_DeviceMaster             = 12,
+        AesKeySlot_Master                   = 13,
+        AesKeySlot_Device                   = 15,
+
+        AesKeySlot_SecmonEnd                = 16,
+
+        /* Used only during boot. */
+        AesKeySlot_Tsec                     = 12,
+        AesKeySlot_TsecRoot                 = 13,
+        AesKeySlot_SecureBoot               = 14,
+        AesKeySlot_SecureStorage            = 15,
+
+        AesKeySlot_MasterKek                = 13,
+        AesKeySlot_DeviceMasterKeySourceKek = 14,
+    };
+
+    enum RsaKeySlot {
+        RsaKeySlot_Temporary  = 0,
+        RsaKeySlot_PrivateKey = 1,
+    };
+
+}
--- a/libraries/libexosphere/include/exosphere/pmc.hpp
+++ b/libraries/libexosphere/include/exosphere/pmc.hpp
@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::pmc {
+
+    enum SecureRegister {
+        SecureRegister_Other          = (1 << 0),
+        SecureRegister_DramParameters = (1 << 1),
+        SecureRegister_ResetVector    = (1 << 2),
+        SecureRegister_Carveout       = (1 << 3),
+        SecureRegister_CmacWrite      = (1 << 4),
+        SecureRegister_CmacRead       = (1 << 5),
+        SecureRegister_KeySourceWrite = (1 << 6),
+        SecureRegister_KeySourceRead  = (1 << 7),
+        SecureRegister_Srk            = (1 << 8),
+
+        SecureRegister_CmacReadWrite      = SecureRegister_CmacRead | SecureRegister_CmacWrite,
+        SecureRegister_KeySourceReadWrite = SecureRegister_KeySourceRead | SecureRegister_KeySourceWrite,
+    };
+
+    void SetRegisterAddress(uintptr_t address);
+
+    void InitializeRandomScratch();
+
+    void LockSecureRegister(SecureRegister reg);
+
+    enum class LockState {
+        Locked         = 0,
+        NotLocked        = 1,
+        PartiallyLocked = 2,
+    };
+
+    LockState GetSecureRegisterLockState(SecureRegister reg);
+
+}
--- a/libraries/libexosphere/include/exosphere/pmic.hpp
+++ b/libraries/libexosphere/include/exosphere/pmic.hpp
@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::pmic {
+
+    enum Regulator {
+        /* Erista regulators. */
+        Regulator_Erista_Max77621   = 0, /* Device code 0x3A000001 */
+
+        /* Mariko regulators. */
+        Regulator_Mariko_Max77812_A = 1, /* Device code 0x3A000002 */
+        Regulator_Mariko_Max77812_B = 2, /* Device code 0x3A000006 */
+    };
+
+    void EnableVddCpu(Regulator regulator);
+    void DisableVddCpu(Regulator regulator);
+
+}
--- a/libraries/libexosphere/include/exosphere/reg.hpp
+++ b/libraries/libexosphere/include/exosphere/reg.hpp
@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::reg {
+
+    using BitsValue = std::tuple<u32, u32, u32>;
+    using BitsMask  = std::tuple<u32, u32>;
+
+    constexpr ALWAYS_INLINE u32 GetOffset(const BitsMask v)  { return std::get<0>(v); }
+    constexpr ALWAYS_INLINE u32 GetOffset(const BitsValue v) { return std::get<0>(v); }
+    constexpr ALWAYS_INLINE u32 GetWidth(const BitsMask v)   { return std::get<1>(v); }
+    constexpr ALWAYS_INLINE u32 GetWidth(const BitsValue v)  { return std::get<1>(v); }
+    constexpr ALWAYS_INLINE u32 GetValue(const BitsValue v)  { return std::get<2>(v); }
+
+    constexpr ALWAYS_INLINE u32 EncodeMask(const BitsMask v) {
+        return (~0u >> (BITSIZEOF(u32) - GetWidth(v))) << GetOffset(v);
+    }
+
+    constexpr ALWAYS_INLINE u32 EncodeMask(const BitsValue v) {
+        return (~0u >> (BITSIZEOF(u32) - GetWidth(v))) << GetOffset(v);
+    }
+
+    constexpr ALWAYS_INLINE u32 EncodeValue(const BitsValue v) {
+        return ((GetValue(v) << GetOffset(v)) & EncodeMask(v));
+    }
+
+    template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
+    constexpr ALWAYS_INLINE u32 Encode(const Values... values) {
+        return (EncodeValue(values) | ...);
+    }
+
+    ALWAYS_INLINE void Write(volatile u32 *reg, u32 val) { *reg = val; }
+    ALWAYS_INLINE void Write(volatile u32 &reg, u32 val) {  reg = val; }
+    ALWAYS_INLINE void Write(uintptr_t reg, u32 val) { Write(reinterpret_cast<volatile u32 *>(reg), val); }
+
+    template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
+    ALWAYS_INLINE void Write(volatile u32 *reg, const Values... values) { return Write(reg, (EncodeValue(values) | ...)); }
+
+    template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
+    ALWAYS_INLINE void Write(volatile u32 &reg, const Values... values) { return Write(reg, (EncodeValue(values) | ...)); }
+
+    template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
+    ALWAYS_INLINE void Write(uintptr_t reg, const Values... values)     { return Write(reg, (EncodeValue(values) | ...)); }
+
+    ALWAYS_INLINE u32 Read(volatile u32 *reg) { return *reg; }
+    ALWAYS_INLINE u32 Read(volatile u32 &reg) { return  reg; }
+    ALWAYS_INLINE u32 Read(uintptr_t reg) { return Read(reinterpret_cast<volatile u32 *>(reg)); }
+
+    ALWAYS_INLINE u32 Read(volatile u32 *reg, u32 mask) { return *reg & mask; }
+    ALWAYS_INLINE u32 Read(volatile u32 &reg, u32 mask) { return  reg & mask; }
+    ALWAYS_INLINE u32 Read(uintptr_t reg, u32 mask) { return Read(reinterpret_cast<volatile u32 *>(reg), mask); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE u32 Read(volatile u32 *reg, const Masks... masks) { return Read(reg, (EncodeMask(masks) | ...)); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE u32 Read(volatile u32 &reg, const Masks... masks) { return Read(reg, (EncodeMask(masks) | ...)); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE u32 Read(uintptr_t reg, const Masks... masks)     { return Read(reg, (EncodeMask(masks) | ...)); }
+
+    template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
+    ALWAYS_INLINE bool HasValue(volatile u32 *reg, const Values... values) { return Read(reg, (EncodeMask(values) | ...)) == Encode(values...); }
+
+    template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
+    ALWAYS_INLINE bool HasValue(volatile u32 &reg, const Values... values) { return Read(reg, (EncodeMask(values) | ...)) == Encode(values...); }
+
+    template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
+    ALWAYS_INLINE bool HasValue(uintptr_t reg, const Values... values) { return Read(reg, (EncodeMask(values) | ...)) == Encode(values...); }
+
+    ALWAYS_INLINE void ReadWrite(volatile u32 *reg, u32 val, u32 mask) { *reg = (*reg & (~mask)) | (val & mask); }
+    ALWAYS_INLINE void ReadWrite(volatile u32 &reg, u32 val, u32 mask) {  reg = ( reg & (~mask)) | (val & mask); }
+    ALWAYS_INLINE void ReadWrite(uintptr_t reg, u32 val, u32 mask) { ReadWrite(reinterpret_cast<volatile u32 *>(reg), val, mask); }
+
+    template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
+    ALWAYS_INLINE void ReadWrite(volatile u32 *reg, const Values... values) { return ReadWrite(reg, (EncodeValue(values) | ...), (EncodeMask(values) | ...)); }
+
+    template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
+    ALWAYS_INLINE void ReadWrite(volatile u32 &reg, const Values... values) { return ReadWrite(reg, (EncodeValue(values) | ...), (EncodeMask(values) | ...)); }
+
+    template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
+    ALWAYS_INLINE void ReadWrite(uintptr_t reg, const Values... values)     { return ReadWrite(reg, (EncodeValue(values) | ...), (EncodeMask(values) | ...)); }
+
+    ALWAYS_INLINE void SetBits(volatile u32 *reg, u32 mask) { *reg = *reg | mask; }
+    ALWAYS_INLINE void SetBits(volatile u32 &reg, u32 mask) {  reg =  reg | mask; }
+    ALWAYS_INLINE void SetBits(uintptr_t reg, u32 mask) { SetBits(reinterpret_cast<volatile u32 *>(reg), mask); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE void SetBits(volatile u32 *reg, const Masks... masks) { return SetBits(reg, (EncodeMask(masks) | ...)); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE void SetBits(volatile u32 &reg, const Masks... masks) { return SetBits(reg, (EncodeMask(masks) | ...)); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE void SetBits(uintptr_t reg, const Masks... masks)     { return SetBits(reg, (EncodeMask(masks) | ...)); }
+
+    ALWAYS_INLINE void ClearBits(volatile u32 *reg, u32 mask) { *reg = *reg & ~mask; }
+    ALWAYS_INLINE void ClearBits(volatile u32 &reg, u32 mask) {  reg =  reg & ~mask; }
+    ALWAYS_INLINE void ClearBits(uintptr_t reg, u32 mask) { ClearBits(reinterpret_cast<volatile u32 *>(reg), mask); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE void ClearBits(volatile u32 *reg, const Masks... masks) { return ClearBits(reg, (EncodeMask(masks) | ...)); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE void ClearBits(volatile u32 &reg, const Masks... masks) { return ClearBits(reg, (EncodeMask(masks) | ...)); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE void ClearBits(uintptr_t reg, const Masks... masks)     { return ClearBits(reg, (EncodeMask(masks) | ...)); }
+
+    ALWAYS_INLINE void MaskBits(volatile u32 *reg, u32 mask) { *reg = *reg & mask; }
+    ALWAYS_INLINE void MaskBits(volatile u32 &reg, u32 mask) {  reg =  reg & mask; }
+    ALWAYS_INLINE void MaskBits(uintptr_t reg, u32 mask) { MaskBits(reinterpret_cast<volatile u32 *>(reg), mask); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE void MaskBits(volatile u32 *reg, const Masks... masks) { return MaskBits(reg, (EncodeMask(masks) | ...)); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE void MaskBits(volatile u32 &reg, const Masks... masks) { return MaskBits(reg, (EncodeMask(masks) | ...)); }
+
+    template<typename... Masks> requires ((sizeof...(Masks) > 0) && (std::is_same<Masks, BitsMask>::value && ...))
+    ALWAYS_INLINE void MaskBits(uintptr_t reg, const Masks... masks)     { return MaskBits(reg, (EncodeMask(masks) | ...)); }
+
+    #define REG_BITS_MASK(OFFSET, WIDTH)         ::ams::reg::BitsMask{OFFSET, WIDTH}
+    #define REG_BITS_VALUE(OFFSET, WIDTH, VALUE) ::ams::reg::BitsValue{OFFSET, WIDTH, VALUE}
+
+    #define REG_NAMED_BITS_MASK(PREFIX, NAME)         REG_BITS_MASK(PREFIX##_##NAME##_OFFSET, PREFIX##_##NAME##_WIDTH)
+    #define REG_NAMED_BITS_VALUE(PREFIX, NAME, VALUE) REG_BITS_VALUE(PREFIX##_##NAME##_OFFSET, PREFIX##_##NAME##_WIDTH, VALUE)
+    #define REG_NAMED_BITS_ENUM(PREFIX, NAME, ENUM)   REG_BITS_VALUE(PREFIX##_##NAME##_OFFSET, PREFIX##_##NAME##_WIDTH, PREFIX##_##NAME##_##ENUM)
+
+    #define REG_NAMED_BITS_ENUM_SEL(PREFIX, NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_BITS_VALUE(PREFIX##_##NAME##_OFFSET, PREFIX##_##NAME##_WIDTH, (__COND__) ? PREFIX##_##NAME##_##TRUE_ENUM : PREFIX##_##NAME##_##FALSE_ENUM)
+
+    #define REG_DEFINE_NAMED_REG(PREFIX, NAME, __OFFSET__, __WIDTH__) \
+        constexpr inline u32 PREFIX##_##NAME##_OFFSET = __OFFSET__;   \
+        constexpr inline u32 PREFIX##_##NAME##_WIDTH  = __WIDTH__
+
+    #define REG_DEFINE_NAMED_BIT_ENUM(PREFIX, NAME, __OFFSET__, ZERO, ONE) \
+        REG_DEFINE_NAMED_REG(PREFIX, NAME, __OFFSET__, 1);                 \
+                                                                           \
+        enum PREFIX##_##NAME {                                             \
+            PREFIX##_##NAME##_##ZERO = 0,                                  \
+            PREFIX##_##NAME##_##ONE  = 1,                                  \
+        };
+
+    #define REG_DEFINE_NAMED_TWO_BIT_ENUM(PREFIX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE) \
+        REG_DEFINE_NAMED_REG(PREFIX, NAME, __OFFSET__, 2);                                 \
+                                                                                           \
+        enum PREFIX##_##NAME {                                                             \
+            PREFIX##_##NAME##_##ZERO   = 0,                                                \
+            PREFIX##_##NAME##_##ONE    = 1,                                                \
+            PREFIX##_##NAME##_##TWO    = 2,                                                \
+            PREFIX##_##NAME##_##THREE  = 3,                                                \
+        };
+
+    #define REG_DEFINE_NAMED_THREE_BIT_ENUM(PREFIX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) \
+        REG_DEFINE_NAMED_REG(PREFIX, NAME, __OFFSET__, 3);                                                           \
+                                                                                                                     \
+        enum PREFIX##_##NAME {                                                                                       \
+            PREFIX##_##NAME##_##ZERO   = 0,                                                                          \
+            PREFIX##_##NAME##_##ONE    = 1,                                                                          \
+            PREFIX##_##NAME##_##TWO    = 2,                                                                          \
+            PREFIX##_##NAME##_##THREE  = 3,                                                                          \
+            PREFIX##_##NAME##_##FOUR   = 4,                                                                          \
+            PREFIX##_##NAME##_##FIVE   = 5,                                                                          \
+            PREFIX##_##NAME##_##SIX    = 6,                                                                          \
+            PREFIX##_##NAME##_##SEVEN  = 7,                                                                          \
+        };
+
+    #define REG_DEFINE_NAMED_FOUR_BIT_ENUM(PREFIX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) \
+        REG_DEFINE_NAMED_REG(PREFIX, NAME, __OFFSET__, 4);                                                                                                                         \
+                                                                                                                                                                                   \
+        enum PREFIX##_##NAME {                                                                                                                                                     \
+            PREFIX##_##NAME##_##ZERO     =  0,                                                                                                                                     \
+            PREFIX##_##NAME##_##ONE      =  1,                                                                                                                                     \
+            PREFIX##_##NAME##_##TWO      =  2,                                                                                                                                     \
+            PREFIX##_##NAME##_##THREE    =  3,                                                                                                                                     \
+            PREFIX##_##NAME##_##FOUR     =  4,                                                                                                                                     \
+            PREFIX##_##NAME##_##FIVE     =  5,                                                                                                                                     \
+            PREFIX##_##NAME##_##SIX      =  6,                                                                                                                                     \
+            PREFIX##_##NAME##_##SEVEN    =  7,                                                                                                                                     \
+            PREFIX##_##NAME##_##EIGHT    =  8,                                                                                                                                     \
+            PREFIX##_##NAME##_##NINE     =  9,                                                                                                                                     \
+            PREFIX##_##NAME##_##TEN      = 10,                                                                                                                                     \
+            PREFIX##_##NAME##_##ELEVEN   = 11,                                                                                                                                     \
+            PREFIX##_##NAME##_##TWELVE   = 12,                                                                                                                                     \
+            PREFIX##_##NAME##_##THIRTEEN = 13,                                                                                                                                     \
+            PREFIX##_##NAME##_##FOURTEEN = 14,                                                                                                                                     \
+            PREFIX##_##NAME##_##FIFTEEN  = 15,                                                                                                                                     \
+        };
+
+}
--- a/libraries/libexosphere/include/exosphere/se.hpp
+++ b/libraries/libexosphere/include/exosphere/se.hpp
@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#include <exosphere/se/se_common.hpp>
+#include <exosphere/se/se_management.hpp>
+#include <exosphere/se/se_aes.hpp>
+#include <exosphere/se/se_rsa.hpp>
+#include <exosphere/se/se_rng.hpp>
+#include <exosphere/se/se_suspend.hpp>
--- a/libraries/libexosphere/include/exosphere/se/se_aes.hpp
+++ b/libraries/libexosphere/include/exosphere/se/se_aes.hpp
@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/se/se_common.hpp>
+
+namespace ams::se {
+
+    constexpr inline int AesKeySlotCount = 16;
+    constexpr inline size_t AesBlockSize = crypto::AesEncryptor128::BlockSize;
+
+    void ClearAesKeySlot(int slot);
+    void LockAesKeySlot(int slot, u32 flags);
+
+    void SetAesKey(int slot, const void *key, size_t key_size);
+
+    void SetEncryptedAesKey128(int dst_slot, int kek_slot, const void *key, size_t key_size);
+    void SetEncryptedAesKey256(int dst_slot, int kek_slot, const void *key, size_t key_size);
+
+    void EncryptAes128(void *dst, size_t dst_size, int slot, const void *src, size_t src_size);
+    void DecryptAes128(void *dst, size_t dst_size, int slot, const void *src, size_t src_size);
+
+}
--- a/libraries/libexosphere/include/exosphere/se/se_common.hpp
+++ b/libraries/libexosphere/include/exosphere/se/se_common.hpp
@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::secmon {
+
+    u8 *GetSecurityEngineEphemeralWorkBlock();
+
+}
+
+namespace ams::se {
+
+    using DoneHandler = void(*)();
+
+    enum KeySlotLockFlags {
+        KeySlotLockFlags_None            = 0,
+        KeySlotLockFlags_KeyRead         = (1u << 0),
+        KeySlotLockFlags_KeyWrite        = (1u << 1),
+        KeySlotLockFlags_OriginalIvRead  = (1u << 2),
+        KeySlotLockFlags_OriginalIvWrite = (1u << 3),
+        KeySlotLockFlags_UpdatedIvRead   = (1u << 4),
+        KeySlotLockFlags_UpdatedIvWrite  = (1u << 5),
+        KeySlotLockFlags_KeyUse          = (1u << 6),
+        KeySlotLockFlags_DstKeyTableOnly = (1u << 7),
+        KeySlotLockFlags_PerKey          = (1u << 8),
+
+        KeySlotLockFlags_AllReadLock = (KeySlotLockFlags_KeyRead | KeySlotLockFlags_OriginalIvRead | KeySlotLockFlags_UpdatedIvRead),
+        KeySlotLockFlags_AllLockKek  = 0x1FF,
+        KeySlotLockFlags_AllLockKey  = (KeySlotLockFlags_AllLockKek & ~KeySlotLockFlags_DstKeyTableOnly),
+
+        KeySlotLockFlags_EristaMask  = 0x7F,
+        KeySlotLockFlags_MarikoMask  = 0xFF,
+    };
+
+    ALWAYS_INLINE u8 *GetEphemeralWorkBlock() {
+        return ::ams::secmon::GetSecurityEngineEphemeralWorkBlock();
+    }
+
+}
--- a/libraries/libexosphere/include/exosphere/se/se_management.hpp
+++ b/libraries/libexosphere/include/exosphere/se/se_management.hpp
@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::se {
+
+    void SetRegisterAddress(uintptr_t address);
+
+    void Initialize();
+
+    void SetSecure(bool secure);
+    void SetTzramSecure();
+    void SetPerKeySecure();
+
+    void Lockout();
+
+    void HandleInterrupt();
+
+}
--- a/libraries/libexosphere/include/exosphere/se/se_rng.hpp
+++ b/libraries/libexosphere/include/exosphere/se/se_rng.hpp
@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::se {
+
+    void InitializeRandom();
+
+    void GenerateRandomBytes(void *dst, size_t size);
+    void SetRandomKey(int slot);
+
+    void GenerateSrk();
+
+}
--- a/libraries/libexosphere/include/exosphere/se/se_rsa.hpp
+++ b/libraries/libexosphere/include/exosphere/se/se_rsa.hpp
@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::se {
+
+    constexpr inline int RsaKeySlotCount = 2;
+    constexpr inline int RsaSize         = 0x100;
+
+    void ClearRsaKeySlot(int slot);
+    void LockRsaKeySlot(int slot, u32 flags);
+
+    void SetRsaKey(int slot, const void *mod, size_t mod_size, const void *exp, size_t exp_size);
+
+}
--- a/libraries/libexosphere/include/exosphere/se/se_suspend.hpp
+++ b/libraries/libexosphere/include/exosphere/se/se_suspend.hpp
@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/se/se_aes.hpp>
+#include <exosphere/se/se_rsa.hpp>
+
+namespace ams::se {
+
+    /* 256-bit AES keyslots are two 128-bit keys. */
+    constexpr inline int AesKeySlotPartCount = 2;
+
+    /* RSA keys are both a modulus and an exponent. */
+    constexpr inline int RsaKeySlotPartCount = 2;
+
+    constexpr inline size_t StickyBitContextSize = 2 * AesBlockSize;
+
+    struct Context {
+        u8 random[AesBlockSize];
+        u8 sticky_bits[StickyBitContextSize / AesBlockSize][AesBlockSize];
+        u8 aes_key[AesKeySlotCount][AesKeySlotPartCount][AesBlockSize];
+        u8 aes_oiv[AesKeySlotCount][AesBlockSize];
+        u8 aes_uiv[AesKeySlotCount][AesBlockSize];
+        u8 rsa_key[RsaKeySlotCount][RsaKeySlotPartCount][RsaSize / AesBlockSize][AesBlockSize];
+        u8 fixed_pattern[AesBlockSize];
+    };
+    static_assert(sizeof(Context) == 0x840);
+    static_assert(util::is_pod<Context>::value);
+
+    struct StickyBits {
+        u8 se_security;
+        u8 tzram_security;
+        u16 crypto_security_perkey;
+        u8 crypto_keytable_access[AesKeySlotCount];
+        u8 rsa_security_perkey;
+        u8 rsa_keytable_access[RsaKeySlotCount];
+    };
+    static_assert(util::is_pod<StickyBits>::value);
+
+    bool ValidateStickyBits(const StickyBits &bits);
+
+}
--- a/libraries/libexosphere/include/exosphere/secmon.hpp
+++ b/libraries/libexosphere/include/exosphere/secmon.hpp
@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/secmon/secmon_memory_layout.hpp>
+#include <exosphere/secmon/secmon_configuration_context.hpp>
+#include <exosphere/secmon/secmon_volatile_context.hpp>
--- a/libraries/libexosphere/include/exosphere/secmon/secmon_configuration_context.arch.arm64.hpp
+++ b/libraries/libexosphere/include/exosphere/secmon/secmon_configuration_context.arch.arm64.hpp
@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/pkg1.hpp>
+#include <exosphere/se.hpp>
+#include <exosphere/secmon/secmon_monitor_context.hpp>
+
+namespace ams::secmon {
+
+    struct ConfigurationContext {
+        union {
+            SecureMonitorConfiguration secmon_cfg;
+            u8 _raw_exosphere_config[0x80];
+        };
+        union {
+            EmummcConfiguration emummc_cfg;
+            u8 _raw_emummc_config[0x120];
+        };
+        union {
+            u8 _misc_data[0x400 - sizeof(_raw_exosphere_config) - sizeof(_raw_emummc_config)];
+        };
+        u8 sealed_device_keys[pkg1::KeyGeneration_Max][se::AesBlockSize];
+        u8 sealed_master_keys[pkg1::KeyGeneration_Max][se::AesBlockSize];
+        pkg1::BootConfig boot_config;
+        u8 rsa_private_exponents[4][se::RsaSize];
+    };
+    static_assert(sizeof(ConfigurationContext) == 0x1000);
+    static_assert(util::is_pod<ConfigurationContext>::value);
+    static_assert(offsetof(ConfigurationContext, sealed_device_keys) == 0x400);
+
+    namespace impl {
+
+        ALWAYS_INLINE uintptr_t GetConfigurationContextAddress() {
+            register uintptr_t x18 asm("x18");
+            __asm__ __volatile__("" : [x18]"=r"(x18));
+            return x18;
+        }
+
+        ALWAYS_INLINE ConfigurationContext &GetConfigurationContext() {
+            return *reinterpret_cast<ConfigurationContext *>(GetConfigurationContextAddress());
+        }
+
+        ALWAYS_INLINE u8 *GetMasterKeyStorage(int generation) {
+            return GetConfigurationContext().sealed_master_keys[generation];
+        }
+
+        ALWAYS_INLINE u8 *GetDeviceMasterKeyStorage(int generation) {
+            return GetConfigurationContext().sealed_device_keys[generation];
+        }
+
+        ALWAYS_INLINE u8 *GetRsaPrivateExponentStorage(int which) {
+            return GetConfigurationContext().rsa_private_exponents[which];
+        }
+
+        ALWAYS_INLINE void SetKeyGeneration(int generation) {
+            GetConfigurationContext().secmon_cfg.key_generation = generation;
+        }
+
+    }
+
+    ALWAYS_INLINE const ConfigurationContext &GetConfigurationContext() {
+        return *reinterpret_cast<const ConfigurationContext *>(impl::GetConfigurationContextAddress());
+    }
+
+    ALWAYS_INLINE const SecureMonitorConfiguration &GetSecmonConfiguration() {
+        return GetConfigurationContext().secmon_cfg;
+    }
+
+    ALWAYS_INLINE const EmummcConfiguration &GetEmummcConfiguration() {
+        return GetConfigurationContext().emummc_cfg;
+    }
+
+    ALWAYS_INLINE const pkg1::BootConfig &GetBootConfig() {
+        return GetConfigurationContext().boot_config;
+    }
+
+    ALWAYS_INLINE ams::TargetFirmware GetTargetFirmware() {
+        return GetSecmonConfiguration().GetTargetFirmware();
+    }
+
+    ALWAYS_INLINE int GetKeyGeneration() {
+        return GetSecmonConfiguration().GetKeyGeneration();
+    }
+
+}
--- a/libraries/libexosphere/include/exosphere/secmon/secmon_configuration_context.hpp
+++ b/libraries/libexosphere/include/exosphere/secmon/secmon_configuration_context.hpp
@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#if   defined(ATMOSPHERE_ARCH_ARM64)
+    #include <exosphere/secmon/secmon_configuration_context.arch.arm64.hpp>
+#elif defined(ATMOSPHERE_ARCH_ARM)
+    /* Nothing to include. */
+#else
+    #error "Unknown architecture for secmon::ConfigurationContext.hpp"
+#endif
--- a/libraries/libexosphere/include/exosphere/secmon/secmon_emummc_context.hpp
+++ b/libraries/libexosphere/include/exosphere/secmon/secmon_emummc_context.hpp
@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::secmon {
+
+    enum EmummcType : u32 {
+        EmummcType_None      = 0,
+        EmummcType_Partition = 1,
+        EmummcType_File      = 2,
+    };
+
+    enum EmummcMmc {
+        EmummcMmc_Nand = 0,
+        EmummcMmc_Sd   = 1,
+        EmummcMmc_Gc   = 2,
+    };
+
+    constexpr inline size_t EmummcFilePathLengthMax = 0x80;
+
+    struct EmummcFilePath {
+        char str[EmummcFilePathLengthMax];
+    };
+    static_assert(util::is_pod<EmummcFilePath>::value);
+    static_assert(sizeof(EmummcFilePath) == EmummcFilePathLengthMax);
+
+    struct EmummcBaseConfiguration {
+        static constexpr u32 Magic = util::FourCC<'E','F','S','0'>::Code;
+
+        u32 magic;
+        EmummcType type;
+        u32 id;
+        u32 fs_version;
+    };
+    static_assert(util::is_pod<EmummcBaseConfiguration>::value);
+    static_assert(sizeof(EmummcBaseConfiguration) == 0x10);
+
+    struct EmummcPartitionConfiguration {
+        u64 start_sector;
+    };
+    static_assert(util::is_pod<EmummcPartitionConfiguration>::value);
+
+    struct EmummcFileConfiguration {
+        EmummcFilePath path;
+    };
+    static_assert(util::is_pod<EmummcFileConfiguration>::value);
+
+    struct EmummcConfiguration {
+        EmummcBaseConfiguration base_cfg;
+        union {
+            EmummcPartitionConfiguration partition_cfg;
+            EmummcFileConfiguration file_cfg;
+        };
+        EmummcFilePath emu_dir_path;
+    };
+    static_assert(util::is_pod<EmummcConfiguration>::value);
+    static_assert(sizeof(EmummcConfiguration) <= 0x200);
+
+}
--- a/libraries/libexosphere/include/exosphere/secmon/secmon_memory_layout.hpp
+++ b/libraries/libexosphere/include/exosphere/secmon/secmon_memory_layout.hpp
@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/mmu.hpp>
+
+namespace ams::secmon {
+
+    using Address = u64;
+
+    struct MemoryRegion {
+        Address start_address;
+        Address end_address;
+
+        constexpr MemoryRegion(Address address, size_t size) : start_address(address), end_address(address + size) {
+            if (end_address < start_address) {
+                __builtin_unreachable();
+            }
+        }
+
+        constexpr Address GetStartAddress() const {
+            return this->start_address;
+        }
+
+        constexpr Address GetAddress() const {
+            return this->GetStartAddress();
+        }
+
+        constexpr Address GetEndAddress() const {
+            return this->end_address;
+        }
+
+        constexpr Address GetLastAddress() const {
+            return this->end_address - 1;
+        }
+
+        constexpr size_t GetSize() const {
+            return this->end_address - this->start_address;
+        }
+
+        constexpr bool Contains(Address address, size_t size) const {
+            return this->start_address <= address && (address + size - 1) <= this->GetLastAddress();
+        }
+
+        constexpr bool Contains(const MemoryRegion &rhs) const {
+            return this->Contains(rhs.GetStartAddress(), rhs.GetSize());
+        }
+
+        template<typename T = void> requires (std::is_same<T, void>::value || util::is_pod<T>::value)
+        ALWAYS_INLINE T *GetPointer() const {
+            return reinterpret_cast<T *>(this->GetAddress());
+        }
+
+        template<typename T = void> requires (std::is_same<T, void>::value || util::is_pod<T>::value)
+        ALWAYS_INLINE T *GetEndPointer() const {
+            return reinterpret_cast<T *>(this->GetEndAddress());
+        }
+    };
+
+    constexpr inline const MemoryRegion MemoryRegionVirtual  = MemoryRegion(UINT64_C(0x1F0000000), 2_MB);
+    constexpr inline const MemoryRegion MemoryRegionPhysical = MemoryRegion(UINT64_C( 0x40000000), 1_GB);
+    constexpr inline const MemoryRegion MemoryRegionDram     = MemoryRegion(UINT64_C( 0x80000000), 2_GB);
+
+    constexpr inline const MemoryRegion MemoryRegionDramDefaultKernelCarveout = MemoryRegion(UINT64_C(0x80060000), UINT64_C(0x1FFE0000));
+    static_assert(MemoryRegionDram.Contains(MemoryRegionDramDefaultKernelCarveout));
+
+    constexpr inline const MemoryRegion MemoryRegionPhysicalIram  = MemoryRegion(UINT64_C(0x40000000), 0x40000);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzram = MemoryRegion(UINT64_C(0x7C010000), 0x10000);
+    static_assert(MemoryRegionPhysical.Contains(MemoryRegionPhysicalIram));
+    static_assert(MemoryRegionPhysical.Contains(MemoryRegionPhysicalTzram));
+
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramVolatile(UINT64_C(0x7C010000),  0x2000);
+    static_assert(MemoryRegionPhysicalTzram.Contains(MemoryRegionPhysicalTzramVolatile));
+
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramNonVolatile(UINT64_C(0x7C012000),  0xE000);
+    static_assert(MemoryRegionPhysicalTzram.Contains(MemoryRegionPhysicalTzramNonVolatile));
+
+    static_assert(MemoryRegionPhysicalTzram.GetSize() == MemoryRegionPhysicalTzramNonVolatile.GetSize() + MemoryRegionPhysicalTzramVolatile.GetSize());
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualL1  = MemoryRegion(util::AlignDown(MemoryRegionVirtual.GetAddress(),  mmu::L1EntrySize), mmu::L1EntrySize);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalL1 = MemoryRegion(util::AlignDown(MemoryRegionPhysical.GetAddress(), mmu::L1EntrySize), mmu::L1EntrySize);
+    static_assert(MemoryRegionVirtualL1.Contains(MemoryRegionVirtual));
+    static_assert(MemoryRegionPhysicalL1.Contains(MemoryRegionPhysical));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualL2       = MemoryRegion(util::AlignDown(MemoryRegionVirtual.GetAddress(),       mmu::L2EntrySize), mmu::L2EntrySize);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalIramL2  = MemoryRegion(util::AlignDown(MemoryRegionPhysicalIram.GetAddress(),  mmu::L2EntrySize), mmu::L2EntrySize);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramL2 = MemoryRegion(util::AlignDown(MemoryRegionPhysicalTzram.GetAddress(), mmu::L2EntrySize), mmu::L2EntrySize);
+    static_assert(MemoryRegionVirtualL2.Contains(MemoryRegionVirtual));
+    static_assert(MemoryRegionPhysicalIramL2.Contains(MemoryRegionPhysicalIram));
+    static_assert(MemoryRegionPhysicalTzramL2.Contains(MemoryRegionPhysicalTzram));
+
+    constexpr inline const MemoryRegion MemoryRegionPhysicalIramBootCode = MemoryRegion(UINT64_C(0x40020000), 0x20000);
+    static_assert(MemoryRegionPhysicalIram.Contains(MemoryRegionPhysicalIramBootCode));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualDevice = MemoryRegion(UINT64_C(0x1F0040000), UINT64_C(0x40000));
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualDevice));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualDeviceEmpty = MemoryRegion(MemoryRegionVirtualDevice.GetStartAddress(), 0);
+
+    #define AMS_SECMON_FOREACH_DEVICE_REGION(HANDLER, ...)                                                            \
+        HANDLER(GicDistributor,                Empty, UINT64_C(0x50041000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(GicCpuInterface,      GicDistributor, UINT64_C(0x50042000),  UINT64_C(0x2000),  true, ## __VA_ARGS__) \
+        HANDLER(Uart,                GicCpuInterface, UINT64_C(0x70006000),  UINT64_C(0x1000), false, ## __VA_ARGS__) \
+        HANDLER(ClkRst,                         Uart, UINT64_C(0x60006000),  UINT64_C(0x1000), false, ## __VA_ARGS__) \
+        HANDLER(RtcPmc,                       ClkRst, UINT64_C(0x7000E000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(Timer,                        RtcPmc, UINT64_C(0x60005000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(System,                        Timer, UINT64_C(0x6000C000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(SecurityEngine,               System, UINT64_C(0x70012000),  UINT64_C(0x2000),  true, ## __VA_ARGS__) \
+        HANDLER(SecurityEngine2,      SecurityEngine, UINT64_C(0x70412000),  UINT64_C(0x2000),  true, ## __VA_ARGS__) \
+        HANDLER(SysCtr0,             SecurityEngine2, UINT64_C(0x700F0000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(MemoryController,            SysCtr0, UINT64_C(0x70019000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(FuseKFuse,          MemoryController, UINT64_C(0x7000F000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(ApbMisc,                   FuseKFuse, UINT64_C(0x70000000),  UINT64_C(0x4000),  true, ## __VA_ARGS__) \
+        HANDLER(FlowController,              ApbMisc, UINT64_C(0x60007000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(BootloaderParams,     FlowController, UINT64_C(0x40000000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(I2c5,               BootloaderParams, UINT64_C(0x7000D000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(Gpio,                           I2c5, UINT64_C(0x6000D000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(I2c1,                           Gpio, UINT64_C(0x7000C000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(ExceptionVectors,               I2c1, UINT64_C(0x6000F000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(MemoryController0,  ExceptionVectors, UINT64_C(0x7001C000),  UINT64_C(0x1000),  true, ## __VA_ARGS__) \
+        HANDLER(MemoryController1, MemoryController0, UINT64_C(0x7001D000),  UINT64_C(0x1000),  true, ## __VA_ARGS__)
+
+    #define DEFINE_DEVICE_REGION(_NAME_, _PREV_, _ADDRESS_, _SIZE_, _SECURE_)                                                                                      \
+        constexpr inline const MemoryRegion MemoryRegionVirtualDevice##_NAME_  = MemoryRegion(MemoryRegionVirtualDevice##_PREV_.GetEndAddress() + 0x1000, _SIZE_); \
+        constexpr inline const MemoryRegion MemoryRegionPhysicalDevice##_NAME_ = MemoryRegion(_ADDRESS_, _SIZE_);                                                  \
+        static_assert(MemoryRegionVirtualDevice.Contains(MemoryRegionVirtualDevice##_NAME_));                                                                      \
+        static_assert(MemoryRegionPhysical.Contains(MemoryRegionPhysicalDevice##_NAME_));
+
+    AMS_SECMON_FOREACH_DEVICE_REGION(DEFINE_DEVICE_REGION)
+
+    #undef DEFINE_DEVICE_REGION
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualDeviceFuses = MemoryRegion(MemoryRegionVirtualDeviceFuseKFuse.GetAddress() + 0x800, 0x400);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDeviceFuses = MemoryRegion(MemoryRegionPhysicalDeviceFuseKFuse.GetAddress() + 0x800, 0x400);
+    static_assert(MemoryRegionVirtualDeviceFuseKFuse.Contains(MemoryRegionVirtualDeviceFuses));
+    static_assert(MemoryRegionPhysicalDeviceFuseKFuse.Contains(MemoryRegionPhysicalDeviceFuses));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualDeviceActivityMonitor = MemoryRegion(MemoryRegionVirtualDeviceSystem.GetAddress() + 0x800, 0x400);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDeviceActivityMonitor = MemoryRegion(MemoryRegionPhysicalDeviceSystem.GetAddress() + 0x800, 0x400);
+    static_assert(MemoryRegionVirtualDeviceSystem.Contains(MemoryRegionVirtualDeviceActivityMonitor));
+    static_assert(MemoryRegionPhysicalDeviceSystem.Contains(MemoryRegionPhysicalDeviceActivityMonitor));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualDeviceUartA  = MemoryRegion(MemoryRegionVirtualDeviceUart.GetAddress()  + 0x000, 0x040);
+    constexpr inline const MemoryRegion MemoryRegionVirtualDeviceUartB  = MemoryRegion(MemoryRegionVirtualDeviceUart.GetAddress()  + 0x040, 0x040);
+    constexpr inline const MemoryRegion MemoryRegionVirtualDeviceUartC  = MemoryRegion(MemoryRegionVirtualDeviceUart.GetAddress()  + 0x200, 0x100);
+    static_assert(MemoryRegionVirtualDeviceUart.Contains(MemoryRegionVirtualDeviceUartA));
+    static_assert(MemoryRegionVirtualDeviceUart.Contains(MemoryRegionVirtualDeviceUartB));
+    static_assert(MemoryRegionVirtualDeviceUart.Contains(MemoryRegionVirtualDeviceUartC));
+
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDeviceUartA = MemoryRegion(MemoryRegionPhysicalDeviceUart.GetAddress() + 0x000, 0x040);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDeviceUartB = MemoryRegion(MemoryRegionPhysicalDeviceUart.GetAddress() + 0x040, 0x040);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDeviceUartC = MemoryRegion(MemoryRegionPhysicalDeviceUart.GetAddress() + 0x200, 0x100);
+    static_assert(MemoryRegionPhysicalDeviceUart.Contains(MemoryRegionPhysicalDeviceUartA));
+    static_assert(MemoryRegionPhysicalDeviceUart.Contains(MemoryRegionPhysicalDeviceUartB));
+    static_assert(MemoryRegionPhysicalDeviceUart.Contains(MemoryRegionPhysicalDeviceUartC));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualDevicePmc  = MemoryRegion(MemoryRegionVirtualDeviceRtcPmc.GetAddress()   + 0x400, 0xC00);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDevicePmc  = MemoryRegion(MemoryRegionPhysicalDeviceRtcPmc.GetAddress() + 0x400, 0xC00);
+    static_assert(MemoryRegionVirtualDeviceRtcPmc.Contains(MemoryRegionVirtualDevicePmc));
+    static_assert(MemoryRegionPhysicalDeviceRtcPmc.Contains(MemoryRegionPhysicalDevicePmc));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualTzramReadOnlyAlias  = MemoryRegion(UINT64_C(0x1F00A0000), MemoryRegionPhysicalTzram.GetSize());
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramReadOnlyAlias = MemoryRegion(MemoryRegionPhysicalTzram.GetAddress(), MemoryRegionPhysicalTzram.GetSize());
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramReadOnlyAlias));
+    static_assert(MemoryRegionPhysicalTzram.Contains(MemoryRegionPhysicalTzramReadOnlyAlias));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualTzramProgram(UINT64_C(0x1F00C0000), 0xC000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramProgram));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualTzramProgramExceptionVectors(UINT64_C(0x1F00C0000), 0x800);
+    static_assert(MemoryRegionVirtualTzramProgram.Contains(MemoryRegionVirtualTzramProgramExceptionVectors));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualTzramProgramMain(UINT64_C(0x1F00C0800), 0xB800);
+    static_assert(MemoryRegionVirtualTzramProgram.Contains(MemoryRegionVirtualTzramProgramMain));
+
+    static_assert(MemoryRegionVirtualTzramProgram.GetSize() == MemoryRegionVirtualTzramProgramExceptionVectors.GetSize() + MemoryRegionVirtualTzramProgramMain.GetSize());
+
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramProgram(UINT64_C(0x7C012000),  0xC000);
+    static_assert(MemoryRegionPhysicalTzramNonVolatile.Contains(MemoryRegionPhysicalTzramProgram));
+
+    constexpr inline const Address PhysicalTzramProgramResetVector = MemoryRegionPhysicalTzramProgram.GetAddress() + MemoryRegionVirtualTzramProgramExceptionVectors.GetSize();
+    static_assert(static_cast<u32>(PhysicalTzramProgramResetVector) == PhysicalTzramProgramResetVector);
+
+    constexpr uintptr_t GetPhysicalTzramProgramAddress(uintptr_t virtual_address) {
+        return virtual_address - MemoryRegionVirtualTzramProgram.GetStartAddress() + MemoryRegionPhysicalTzramNonVolatile.GetStartAddress();
+    }
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualIramSc7Work  = MemoryRegion(UINT64_C(0x1F0120000), MemoryRegionPhysicalTzram.GetSize());
+    constexpr inline const MemoryRegion MemoryRegionPhysicalIramSc7Work = MemoryRegion( UINT64_C(0x40020000), MemoryRegionPhysicalTzram.GetSize());
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualIramSc7Work));
+    static_assert(MemoryRegionPhysicalIram.Contains(MemoryRegionPhysicalIramSc7Work));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualIramSc7Firmware  = MemoryRegion(UINT64_C(0x1F0140000), 0x1000);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalIramSc7Firmware = MemoryRegion( UINT64_C(0x40003000), 0x1000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualIramSc7Firmware));
+    static_assert(MemoryRegionPhysicalIram.Contains(MemoryRegionPhysicalIramSc7Firmware));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualDebug = MemoryRegion(UINT64_C(0x1F0160000), 0x10000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualIramSc7Firmware));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualTzramBootCode  = MemoryRegion(UINT64_C(0x1F01C0000), 0x2000);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramBootCode = MemoryRegion( UINT64_C(0x7C010000), 0x2000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramBootCode));
+    static_assert(MemoryRegionPhysicalTzramVolatile.Contains(MemoryRegionPhysicalTzramBootCode));
+
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDramMonitorConfiguration = MemoryRegion( UINT64_C(0x8000F000), 0x1000);
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualDramSecureDataStore  = MemoryRegion(UINT64_C(0x1F0100000), 0x10000);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDramSecureDataStore = MemoryRegion( UINT64_C(0x80010000), 0x10000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualDramSecureDataStore));
+    static_assert(MemoryRegionDram.Contains(MemoryRegionPhysicalDramSecureDataStore));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualDramSecureDataStoreTzram               = MemoryRegion(UINT64_C(0x1F0100000), 0xE000);
+    constexpr inline const MemoryRegion MemoryRegionVirtualDramSecureDataStoreWarmbootFirmware    = MemoryRegion(UINT64_C(0x1F010E000), 0x17C0);
+    constexpr inline const MemoryRegion MemoryRegionVirtualDramSecureDataStoreSecurityEngineState = MemoryRegion(UINT64_C(0x1F010F7C0), 0x0840);
+    static_assert(MemoryRegionVirtualDramSecureDataStore.Contains(MemoryRegionVirtualDramSecureDataStoreTzram));
+    static_assert(MemoryRegionVirtualDramSecureDataStore.Contains(MemoryRegionVirtualDramSecureDataStoreWarmbootFirmware));
+    static_assert(MemoryRegionVirtualDramSecureDataStore.Contains(MemoryRegionVirtualDramSecureDataStoreSecurityEngineState));
+
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDramSecureDataStoreTzram               = MemoryRegion(UINT64_C(0x80010000), 0xE000);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDramSecureDataStoreWarmbootFirmware    = MemoryRegion(UINT64_C(0x8001E000), 0x17C0);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalDramSecureDataStoreSecurityEngineState = MemoryRegion(UINT64_C(0x8001F7C0), 0x0840);
+    static_assert(MemoryRegionPhysicalDramSecureDataStore.Contains(MemoryRegionPhysicalDramSecureDataStoreTzram));
+    static_assert(MemoryRegionPhysicalDramSecureDataStore.Contains(MemoryRegionPhysicalDramSecureDataStoreWarmbootFirmware));
+    static_assert(MemoryRegionPhysicalDramSecureDataStore.Contains(MemoryRegionPhysicalDramSecureDataStoreSecurityEngineState));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualAtmosphereIramPage      = MemoryRegion(UINT64_C(0x1F01F0000), 0x1000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualAtmosphereIramPage));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualAtmosphereUserPage      = MemoryRegion(UINT64_C(0x1F01F2000), 0x1000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualAtmosphereUserPage));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualSmcUserPage             = MemoryRegion(UINT64_C(0x1F01F4000), 0x1000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualSmcUserPage));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualTzramVolatileData       = MemoryRegion(UINT64_C(0x1F01F6000), 0x1000);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramVolatileData      = MemoryRegion( UINT64_C(0x7C010000), 0x1000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramVolatileData));
+    static_assert(MemoryRegionPhysicalTzramVolatile.Contains(MemoryRegionPhysicalTzramVolatileData));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualTzramVolatileStack      = MemoryRegion(UINT64_C(0x1F01F8000), 0x1000);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramVolatileStack     = MemoryRegion( UINT64_C(0x7C011000), 0x1000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramVolatileStack));
+    static_assert(MemoryRegionPhysicalTzramVolatile.Contains(MemoryRegionPhysicalTzramVolatileStack));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualTzramConfigurationData  = MemoryRegion(UINT64_C(0x1F01FA000), 0x1000);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramConfigurationData = MemoryRegion( UINT64_C(0x7C01E000), 0x1000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramConfigurationData));
+    static_assert(MemoryRegionPhysicalTzramNonVolatile.Contains(MemoryRegionPhysicalTzramConfigurationData));
+
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualTzramL1PageTable  = MemoryRegion(UINT64_C(0x1F01FCFC0), 0x40);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramL1PageTable = MemoryRegion( UINT64_C(0x7C01EFC0), 0x40);
+    static_assert(MemoryRegionPhysicalTzramConfigurationData.Contains(MemoryRegionPhysicalTzramL1PageTable));
+
+    constexpr inline const MemoryRegion MemoryRegionVirtualTzramL2L3PageTable  = MemoryRegion(UINT64_C(0x1F01FE000), 0x1000);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramL2L3PageTable = MemoryRegion( UINT64_C(0x7C01F000), 0x1000);
+    static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramL2L3PageTable));
+    static_assert(MemoryRegionPhysicalTzramNonVolatile.Contains(MemoryRegionPhysicalTzramL2L3PageTable));
+
+    constexpr inline const MemoryRegion MemoryRegionPhysicalTzramFullProgramImage = MemoryRegion(0x7C010800, 0xD800);
+    constexpr inline const MemoryRegion MemoryRegionPhysicalIramBootCodeImage     = MemoryRegion(0x40032000, 0xC000);
+
+}
--- a/libraries/libexosphere/include/exosphere/secmon/secmon_monitor_context.hpp
+++ b/libraries/libexosphere/include/exosphere/secmon/secmon_monitor_context.hpp
@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/secmon/secmon_emummc_context.hpp>
+
+namespace ams::secmon {
+
+    enum SecureMonitorConfigurationFlag : u32 {
+        SecureMonitorConfigurationFlag_None                                   = (0u << 0),
+        SecureMonitorConfigurationFlag_IsDevelopmentFunctionEnabledForKernel  = (1u << 1),
+        SecureMonitorConfigurationFlag_IsDevelopmentFunctionEnabledForUser    = (1u << 2),
+        SecureMonitorConfigurationFlag_DisableUserModeExceptionHandlers       = (1u << 3),
+        SecureMonitorConfigurationFlag_EnableUserModePerformanceCounterAccess = (1u << 4),
+        SecureMonitorConfigurationFlag_ShouldUseBlankCalibrationBinary        = (1u << 5),
+        SecureMonitorConfigurationFlag_AllowWritingToCalibrationBinarySysmmc  = (1u << 6),
+
+        SecureMonitorConfigurationFlag_Default = SecureMonitorConfigurationFlag_IsDevelopmentFunctionEnabledForKernel,
+    };
+
+    struct SecureMonitorStorageConfiguration {
+        static constexpr u32 Magic = util::FourCC<'E','X','O','0'>::Code;
+
+        u32 magic;
+        ams::TargetFirmware target_firmware;
+        u32 flags;
+        u32 reserved[5];
+        EmummcConfiguration emummc_cfg;
+
+        constexpr bool IsValid() const { return this->magic == Magic; }
+    };
+    static_assert(util::is_pod<SecureMonitorStorageConfiguration>::value);
+    static_assert(sizeof(SecureMonitorStorageConfiguration) == 0x130);
+
+    struct SecureMonitorConfiguration {
+        ams::TargetFirmware target_firmware;
+        s32 key_generation;
+        u32 flags;
+        u32 reserved[(0x80 - 0x0C) / sizeof(u32)];
+
+        constexpr void CopyFrom(const SecureMonitorStorageConfiguration &storage) {
+            this->target_firmware = storage.target_firmware;
+            this->flags           = storage.flags;
+        }
+
+        constexpr ams::TargetFirmware GetTargetFirmware() const { return this->target_firmware; }
+        constexpr int GetKeyGeneration() const { return this->key_generation; }
+
+        constexpr bool IsDevelopmentFunctionEnabledForKernel()  const { return (this->flags & SecureMonitorConfigurationFlag_IsDevelopmentFunctionEnabledForKernel)  != 0; }
+        constexpr bool IsDevelopmentFunctionEnabledForUser()    const { return (this->flags & SecureMonitorConfigurationFlag_IsDevelopmentFunctionEnabledForUser)    != 0; }
+        constexpr bool DisableUserModeExceptionHandlers()       const { return (this->flags & SecureMonitorConfigurationFlag_DisableUserModeExceptionHandlers)       != 0; }
+        constexpr bool EnableUserModePerformanceCounterAccess() const { return (this->flags & SecureMonitorConfigurationFlag_EnableUserModePerformanceCounterAccess) != 0; }
+        constexpr bool ShouldUseBlankCalibrationBinary()        const { return (this->flags & SecureMonitorConfigurationFlag_ShouldUseBlankCalibrationBinary)        != 0; }
+        constexpr bool AllowWritingToCalibrationBinarySysmmc()  const { return (this->flags & SecureMonitorConfigurationFlag_AllowWritingToCalibrationBinarySysmmc)  != 0; }
+    };
+    static_assert(util::is_pod<SecureMonitorConfiguration>::value);
+    static_assert(sizeof(SecureMonitorConfiguration) == 0x80);
+
+    constexpr inline const SecureMonitorConfiguration DefaultSecureMonitorConfiguration = {
+        .target_firmware = ams::TargetFirmware_Current,
+        .flags           = SecureMonitorConfigurationFlag_Default,
+    };
+
+}
--- a/libraries/libexosphere/include/exosphere/secmon/secmon_volatile_context.hpp
+++ b/libraries/libexosphere/include/exosphere/secmon/secmon_volatile_context.hpp
@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::secmon {
+
+    /* The VolatileStack page is reserved entirely for use for core 3 SMC handling. */
+    constexpr inline const Address Core3SmcStackAddress = MemoryRegionVirtualTzramVolatileStack.GetAddress() + MemoryRegionVirtualTzramVolatileStack.GetSize();
+
+    constexpr inline const size_t CoreExceptionStackSize = 0x80;
+
+    /* Nintendo uses the bottom 0x740 of this as a stack for warmboot setup, and another 0x740 for the core 0/1/2 SMC stacks. */
+    /* This is...wasteful. The warmboot stack is not deep. We will thus save 1K+ of nonvolatile storage by keeping the random cache in here. */
+    struct VolatileData {
+        u8 random_cache[0x400];
+        u8 se_work_block[crypto::AesEncryptor128::BlockSize];
+        u8 reserved_danger_zone[0x30]; /* This memory is "available", but careful consideration must be taken before declaring it used. */
+        u8 warmboot_stack[0x380];
+        u8 core012_smc_stack[0x6C0];
+        u8 core_exception_stacks[3][CoreExceptionStackSize];
+    };
+    static_assert(util::is_pod<VolatileData>::value);
+    static_assert(sizeof(VolatileData) == 0x1000);
+
+    ALWAYS_INLINE VolatileData &GetVolatileData() {
+        return *MemoryRegionVirtualTzramVolatileData.GetPointer<VolatileData>();
+    }
+
+    ALWAYS_INLINE u8 *GetRandomBytesCache() {
+        return GetVolatileData().random_cache;
+    }
+
+    constexpr ALWAYS_INLINE size_t GetRandomBytesCacheSize() {
+        return sizeof(VolatileData::random_cache);
+    }
+
+    ALWAYS_INLINE u8 *GetSecurityEngineEphemeralWorkBlock() {
+        return GetVolatileData().se_work_block;
+    }
+
+    constexpr inline const Address WarmbootStackAddress   = MemoryRegionVirtualTzramVolatileData.GetAddress() + offsetof(VolatileData, warmboot_stack)    + sizeof(VolatileData::warmboot_stack);
+    constexpr inline const Address Core012SmcStackAddress = MemoryRegionVirtualTzramVolatileData.GetAddress() + offsetof(VolatileData, core012_smc_stack) + sizeof(VolatileData::core012_smc_stack);
+
+    constexpr inline const Address Core0ExceptionStackAddress = MemoryRegionVirtualTzramVolatileData.GetAddress() + offsetof(VolatileData, core_exception_stacks) + CoreExceptionStackSize;
+    constexpr inline const Address Core1ExceptionStackAddress = Core0ExceptionStackAddress + CoreExceptionStackSize;
+    constexpr inline const Address Core2ExceptionStackAddress = Core1ExceptionStackAddress + CoreExceptionStackSize;
+
+}
--- a/libraries/libexosphere/include/exosphere/tegra.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra.hpp
@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#include <exosphere/tegra/tegra_ahb_arbc.hpp>
+#include <exosphere/tegra/tegra_apb_misc.hpp>
+#include <exosphere/tegra/tegra_avp_cache.hpp>
+#include <exosphere/tegra/tegra_emc.hpp>
+#include <exosphere/tegra/tegra_evp.hpp>
+#include <exosphere/tegra/tegra_flow_ctlr.hpp>
+#include <exosphere/tegra/tegra_ictlr.hpp>
+#include <exosphere/tegra/tegra_mc.hpp>
+#include <exosphere/tegra/tegra_mselect.hpp>
+#include <exosphere/tegra/tegra_pmc.hpp>
+#include <exosphere/tegra/tegra_sb.hpp>
+#include <exosphere/tegra/tegra_sysctr0.hpp>
+#include <exosphere/tegra/tegra_timer.hpp>
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp
@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#define AHB_ARBC(x) (0x6000c000 + x)
+
+#define AHB_ARBITRATION_DISABLE       (0x004)
+#define AHB_ARBITRATION_PRIORITY_CTRL (0x008)
+#define AHB_MASTER_SWID               (0x018)
+#define AHB_MASTER_SWID_1             (0x038)
+#define AHB_GIZMO_TZRAM               (0x054)
+
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_apb_misc.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_apb_misc.hpp
@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00)
+#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 (0xc04)
+#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 (0xc08)
+
+#define AHB_MISC_REG_BITS_MASK(NAME)                                      REG_NAMED_BITS_MASK    (AHB_MISC, NAME)
+#define AHB_MISC_REG_BITS_VALUE(NAME, VALUE)                              REG_NAMED_BITS_VALUE   (AHB_MISC, NAME, VALUE)
+#define AHB_MISC_REG_BITS_ENUM(NAME, ENUM)                                REG_NAMED_BITS_ENUM    (AHB_MISC, NAME, ENUM)
+#define AHB_MISC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(AHB_MISC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
+
+#define DEFINE_AHB_MISC_REG(NAME, __OFFSET__, __WIDTH__)                                                                                                                  REG_DEFINE_NAMED_REG           (AHB_MISC, NAME, __OFFSET__, __WIDTH__)
+#define DEFINE_AHB_MISC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE)                                                                                                         REG_DEFINE_NAMED_BIT_ENUM      (AHB_MISC, NAME, __OFFSET__, ZERO, ONE)
+#define DEFINE_AHB_MISC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE)                                                                                         REG_DEFINE_NAMED_TWO_BIT_ENUM  (AHB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
+#define DEFINE_AHB_MISC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)                                                               REG_DEFINE_NAMED_THREE_BIT_ENUM(AHB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
+#define DEFINE_AHB_MISC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (AHB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
+
+#define DEFINE_SLAVE_SECURITY_REG(RINDEX, INDEX, NAME) DEFINE_AHB_MISC_REG_BIT_ENUM(SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG##RINDEX##_##NAME##_SECURITY_EN, INDEX, DISABLE, ENABLE)
+
+DEFINE_SLAVE_SECURITY_REG(0, 29, STM);
+DEFINE_SLAVE_SECURITY_REG(0, 24, CEC);
+DEFINE_SLAVE_SECURITY_REG(0, 23, ATOMICS);
+DEFINE_SLAVE_SECURITY_REG(0, 22, LA);
+DEFINE_SLAVE_SECURITY_REG(0, 21, HDA);
+DEFINE_SLAVE_SECURITY_REG(0, 20, SATA);
+DEFINE_SLAVE_SECURITY_REG(0, 16, KFUSE);
+DEFINE_SLAVE_SECURITY_REG(0, 15, FUSE);
+DEFINE_SLAVE_SECURITY_REG(0, 14, SE);
+DEFINE_SLAVE_SECURITY_REG(0, 13, PMC);
+DEFINE_SLAVE_SECURITY_REG(0, 11, RTC);
+DEFINE_SLAVE_SECURITY_REG(0, 10, CSITE);
+DEFINE_SLAVE_SECURITY_REG(0,  9, QSPI);
+DEFINE_SLAVE_SECURITY_REG(0,  8, PWM);
+DEFINE_SLAVE_SECURITY_REG(0,  6, DTV);
+DEFINE_SLAVE_SECURITY_REG(0,  4, APE);
+DEFINE_SLAVE_SECURITY_REG(0,  3, PINMUX_AUX);
+DEFINE_SLAVE_SECURITY_REG(0,  2, SATA_AUX);
+DEFINE_SLAVE_SECURITY_REG(0,  1, MISC_REGS);
+
+DEFINE_SLAVE_SECURITY_REG(1, 31, I2C6);
+DEFINE_SLAVE_SECURITY_REG(1, 30, DVC);
+DEFINE_SLAVE_SECURITY_REG(1, 29, I2C4);
+DEFINE_SLAVE_SECURITY_REG(1, 28, I2C3);
+DEFINE_SLAVE_SECURITY_REG(1, 27, I2C2);
+DEFINE_SLAVE_SECURITY_REG(1, 26, I2C1);
+DEFINE_SLAVE_SECURITY_REG(1, 25, SPI6);
+DEFINE_SLAVE_SECURITY_REG(1, 24, SPI5);
+DEFINE_SLAVE_SECURITY_REG(1, 23, SPI4);
+DEFINE_SLAVE_SECURITY_REG(1, 22, SPI3);
+DEFINE_SLAVE_SECURITY_REG(1, 21, SPI2);
+DEFINE_SLAVE_SECURITY_REG(1, 20, SPI1);
+DEFINE_SLAVE_SECURITY_REG(1, 15, UART_D);
+DEFINE_SLAVE_SECURITY_REG(1, 14, UART_C);
+DEFINE_SLAVE_SECURITY_REG(1, 13, UART_B);
+DEFINE_SLAVE_SECURITY_REG(1, 12, UART_A);
+DEFINE_SLAVE_SECURITY_REG(1, 11, EMCB);
+DEFINE_SLAVE_SECURITY_REG(1, 10, MCB);
+DEFINE_SLAVE_SECURITY_REG(1,  9, EMC1);
+DEFINE_SLAVE_SECURITY_REG(1,  8, MC1);
+DEFINE_SLAVE_SECURITY_REG(1,  5, EMC0);
+DEFINE_SLAVE_SECURITY_REG(1,  4, MC0);
+
+DEFINE_SLAVE_SECURITY_REG(2, 21, FEK);
+DEFINE_SLAVE_SECURITY_REG(2, 20, PKA1);
+DEFINE_SLAVE_SECURITY_REG(2, 19, SE2);
+DEFINE_SLAVE_SECURITY_REG(2, 16, DVFS);
+DEFINE_SLAVE_SECURITY_REG(2, 15, MIPI_CAL);
+DEFINE_SLAVE_SECURITY_REG(2, 14, XUSB_PADCTL);
+DEFINE_SLAVE_SECURITY_REG(2, 13, XUSB_DEV);
+DEFINE_SLAVE_SECURITY_REG(2, 12, XUSB_HOST);
+DEFINE_SLAVE_SECURITY_REG(2, 11, APB2JTAG);
+DEFINE_SLAVE_SECURITY_REG(2, 10, SOC_THERM);
+DEFINE_SLAVE_SECURITY_REG(2,  9, DP2);
+DEFINE_SLAVE_SECURITY_REG(2,  8, DDS);
+DEFINE_SLAVE_SECURITY_REG(2,  7, MIPIBIF);
+DEFINE_SLAVE_SECURITY_REG(2,  3, SDMMC4);
+DEFINE_SLAVE_SECURITY_REG(2,  2, SDMMC3);
+DEFINE_SLAVE_SECURITY_REG(2,  1, SDMMC2);
+DEFINE_SLAVE_SECURITY_REG(2,  0, SDMMC1);
+
+#undef DEFINE_SLAVE_SECURITY_REG
+
+#define SLAVE_SECURITY_REG_BITS_ENUM(RINDEX, NAME, ENUM) AHB_MISC_REG_BITS_ENUM(SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG##RINDEX##_##NAME##_SECURITY_EN, ENUM)
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_avp_cache.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_avp_cache.hpp
@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#define AVP_CACHE_ADDRESS(x) (0x50040000 + x)
+
+#define AVP_CACHE_CONFIG       (0x000)
+
+#define AVP_CACHE_REG_BITS_MASK(NAME)                                      REG_NAMED_BITS_MASK    (AVP_CACHE, NAME)
+#define AVP_CACHE_REG_BITS_VALUE(NAME, VALUE)                              REG_NAMED_BITS_VALUE   (AVP_CACHE, NAME, VALUE)
+#define AVP_CACHE_REG_BITS_ENUM(NAME, ENUM)                                REG_NAMED_BITS_ENUM    (AVP_CACHE, NAME, ENUM)
+#define AVP_CACHE_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(AVP_CACHE, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
+
+#define DEFINE_AVP_CACHE_REG(NAME, __OFFSET__, __WIDTH__)                                                                                                                  REG_DEFINE_NAMED_REG           (AVP_CACHE, NAME, __OFFSET__, __WIDTH__)
+#define DEFINE_AVP_CACHE_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE)                                                                                                         REG_DEFINE_NAMED_BIT_ENUM      (AVP_CACHE, NAME, __OFFSET__, ZERO, ONE)
+#define DEFINE_AVP_CACHE_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE)                                                                                         REG_DEFINE_NAMED_TWO_BIT_ENUM  (AVP_CACHE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
+#define DEFINE_AVP_CACHE_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)                                                               REG_DEFINE_NAMED_THREE_BIT_ENUM(AVP_CACHE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
+#define DEFINE_AVP_CACHE_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (AVP_CACHE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
+
+DEFINE_AVP_CACHE_REG_BIT_ENUM(DISABLE_WB, 10, FALSE, TRUE);
+DEFINE_AVP_CACHE_REG_BIT_ENUM(DISABLE_RB, 11, FALSE, TRUE);
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_emc.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_emc.hpp
@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#define EMC_ADDRESS(x)  (0x7001B000 + x)
+#define EMC0_ADDRESS(x) (0x7001E000 + x)
+#define EMC1_ADDRESS(x) (0x7001F000 + x)
+
+#define EMC_CFG             (0x00C)
+#define EMC_ADR_CFG         (0x010)
+#define EMC_TIMING_CONTROL  (0x028)
+#define EMC_SELF_REF        (0x0E0)
+#define EMC_MRW             (0x0E8)
+#define EMC_FBIO_CFG5       (0x104)
+#define EMC_MRW3            (0x138)
+#define EMC_AUTO_CAL_CONFIG (0x2A4)
+#define EMC_REQ_CTRL        (0x2B0)
+#define EMC_EMC_STATUS      (0x2B4)
+#define EMC_CFG_DIG_DLL     (0x2BC)
+#define EMC_ZCAL_INTERVAL   (0x2E0)
+#define EMC_PMC_SCRATCH3    (0x448)
+#define EMC_FBIO_CFG7       (0x584)
+
+#define EMC_REG_BITS_MASK(NAME)                                      REG_NAMED_BITS_MASK    (EMC, NAME)
+#define EMC_REG_BITS_VALUE(NAME, VALUE)                              REG_NAMED_BITS_VALUE   (EMC, NAME, VALUE)
+#define EMC_REG_BITS_ENUM(NAME, ENUM)                                REG_NAMED_BITS_ENUM    (EMC, NAME, ENUM)
+#define EMC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(EMC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
+
+#define DEFINE_EMC_REG(NAME, __OFFSET__, __WIDTH__)                                                                                                                  REG_DEFINE_NAMED_REG           (EMC, NAME, __OFFSET__, __WIDTH__)
+#define DEFINE_EMC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE)                                                                                                         REG_DEFINE_NAMED_BIT_ENUM      (EMC, NAME, __OFFSET__, ZERO, ONE)
+#define DEFINE_EMC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE)                                                                                         REG_DEFINE_NAMED_TWO_BIT_ENUM  (EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
+#define DEFINE_EMC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)                                                               REG_DEFINE_NAMED_THREE_BIT_ENUM(EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
+#define DEFINE_EMC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
+
+DEFINE_EMC_REG_BIT_ENUM(CFG_DYN_SELF_REF, 28, DISABLED, ENABLED);
+DEFINE_EMC_REG_BIT_ENUM(CFG_DRAM_ACPD,    29, NO_POWERDOWN, ACTIVE_POWERDOWN);
+
+DEFINE_EMC_REG_BIT_ENUM(ADR_CFG_EMEM_NUMDEV, 0, N1, N2);
+
+DEFINE_EMC_REG_BIT_ENUM(TIMING_CONTROL_TIMING_UPDATE, 0, DISABLED, ENABLED);
+
+DEFINE_EMC_REG_BIT_ENUM(SELF_REF_SELF_REF_CMD, 0, DISABLED, ENABLED);
+DEFINE_EMC_REG_BIT_ENUM(SELF_REF_ACTIVE_SELF_REF, 8, DISABLED, ENABLED);
+DEFINE_EMC_REG_TWO_BIT_ENUM(SELF_REF_SREF_DEV_SELECTN, 30, BOTH, DEV1, DEV0, RESERVED);
+
+DEFINE_EMC_REG(MRW_OP,  0, 8);
+DEFINE_EMC_REG(MRW_MA, 16, 8);
+DEFINE_EMC_REG_TWO_BIT_ENUM(MRW_CNT, 26, SHORT, LONG, EXT1, EXT2);
+DEFINE_EMC_REG_TWO_BIT_ENUM(MRW_DEV_SELECTN, 30, BOTH, DEV1, DEV0, RESERVED);
+
+DEFINE_EMC_REG_TWO_BIT_ENUM(FBIO_CFG5_DRAM_TYPE, 0, DDR4, LPDDR4, LPDDR2, DDR2);
+
+DEFINE_EMC_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL,  9, DISABLE, ENABLE);
+DEFINE_EMC_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL,  10, DISABLE, ENABLE);
+DEFINE_EMC_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_START,         31, DISABLE, ENABLE);
+
+DEFINE_EMC_REG(REQ_CTRL_STALL_ALL_READS,  0, 1);
+DEFINE_EMC_REG(REQ_CTRL_STALL_ALL_WRITES, 1, 1);
+
+DEFINE_EMC_REG_TWO_BIT_ENUM(EMC_STATUS_DRAM_IN_SELF_REFRESH, 8, DISABLED, DEV0_ENABLED, DEV1_ENABLED, BOTH_ENABLED);
+
+DEFINE_EMC_REG_BIT_ENUM(EMC_STATUS_DRAM_DEV0_IN_SELF_REFRESH, 8, DISABLED, ENABLED);
+
+DEFINE_EMC_REG_BIT_ENUM(EMC_STATUS_NO_OUTSTANDING_TRANSACTIONS, 2, WAITING, COMPLETED);
+DEFINE_EMC_REG_BIT_ENUM(EMC_STATUS_TIMING_UPDATE_STALLED, 23, DONE, BUSY);
+
+DEFINE_EMC_REG_BIT_ENUM(CFG_DIG_DLL_CFG_DLL_EN, 0, DISABLED, ENABLED);
+
+DEFINE_EMC_REG(ZCAL_INTERVAL_LO,  0, 10);
+DEFINE_EMC_REG(ZCAL_INTERVAL_HI, 10, 14);
+
+DEFINE_EMC_REG(PMC_SCRATCH3_DDR_CNTRL, 0, 19);
+DEFINE_EMC_REG_BIT_ENUM(PMC_SCRATCH3_WEAK_BIAS, 30, DISABLED, ENABLED);
+
+DEFINE_EMC_REG_BIT_ENUM(FBIO_CFG7_CH1_ENABLE, 2, DISABLE, ENABLE);
+
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_evp.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_evp.hpp
@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#define EVP_CPU_RESET_VECTOR (0x100)
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp
@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+
+#define FLOW_CTLR_FLOW_DBG_QUAL        (0x050)
+#define FLOW_CTLR_BPMP_CLUSTER_CONTROL (0x098)
+
+#define FLOW_REG_BITS_MASK(NAME)                                      REG_NAMED_BITS_MASK    (FLOW_CTLR, NAME)
+#define FLOW_REG_BITS_VALUE(NAME, VALUE)                              REG_NAMED_BITS_VALUE   (FLOW_CTLR, NAME, VALUE)
+#define FLOW_REG_BITS_ENUM(NAME, ENUM)                                REG_NAMED_BITS_ENUM    (FLOW_CTLR, NAME, ENUM)
+#define FLOW_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(FLOW_CTLR, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
+
+#define DEFINE_FLOW_REG(NAME, __OFFSET__, __WIDTH__)                                                                                                                  REG_DEFINE_NAMED_REG           (FLOW_CTLR, NAME, __OFFSET__, __WIDTH__)
+#define DEFINE_FLOW_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE)                                                                                                         REG_DEFINE_NAMED_BIT_ENUM      (FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE)
+#define DEFINE_FLOW_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE)                                                                                         REG_DEFINE_NAMED_TWO_BIT_ENUM  (FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
+#define DEFINE_FLOW_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)                                                               REG_DEFINE_NAMED_THREE_BIT_ENUM(FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
+#define DEFINE_FLOW_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
+
+DEFINE_FLOW_REG_BIT_ENUM(FLOW_DBG_QUAL_FIQ2CCPLEX_ENABLE, 28, DISABLE, ENABLE);
+
+DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER,        0, FAST, SLOW);
+DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_CLUSTER_SWITCH_ENABLE, 1, DISABLE, ENABLE);
+DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER_LOCK,   2, DISABLE, ENABLE);
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_ictlr.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_ictlr.hpp
@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#define PRI_ICTLR(n)   (0x60004000 + n)
+#define SEC_ICTLR(n)   (0x60004100 + n)
+#define TRI_ICTLR(n)   (0x60004200 + n)
+#define QUAD_ICTLR(n)  (0x60004300 + n)
+#define PENTA_ICTLR(n) (0x60004400 + n)
+#define HEXA_ICTLR(n)  (0x60004500 + n)
+
+#define ICTLR_COP_IER_CLR   (0x038)
+
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_mc.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_mc.hpp
@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/reg.hpp>
+
+#define MC_INTSTATUS                                        (0x000)
+#define MC_INTMASK                                          (0x004)
+#define MC_ERR_STATUS                                       (0x008)
+#define MC_ERR_ADR                                          (0x00c)
+#define MC_SMMU_CONFIG                                      (0x010)
+#define MC_SMMU_TLB_CONFIG                                  (0x014)
+#define MC_SMMU_PTC_CONFIG                                  (0x018)
+#define MC_SMMU_PTB_ASID                                    (0x01c)
+#define MC_SMMU_PTB_DATA                                    (0x020)
+#define MC_SMMU_TLB_FLUSH                                   (0x030)
+#define MC_SMMU_PTC_FLUSH                                   (0x034)
+
+#define MC_SECURITY_CFG0                                    (0x070)
+#define MC_SECURITY_CFG1                                    (0x074)
+#define MC_SECURITY_CFG3                                    (0x9BC)
+
+#define MC_SMMU_TRANSLATION_ENABLE_0                        (0x228)
+#define MC_SMMU_TRANSLATION_ENABLE_1                        (0x22C)
+#define MC_SMMU_TRANSLATION_ENABLE_2                        (0x230)
+#define MC_SMMU_TRANSLATION_ENABLE_3                        (0x234)
+#define MC_SMMU_TRANSLATION_ENABLE_4                        (0xB98)
+
+#define MC_SMMU_ASID_SECURITY                               (0x038)
+#define MC_SMMU_ASID_SECURITY_1                             (0x03c)
+#define MC_SMMU_ASID_SECURITY_2                             (0x9e0)
+#define MC_SMMU_ASID_SECURITY_3                             (0x9e4)
+#define MC_SMMU_ASID_SECURITY_4                             (0x9e8)
+#define MC_SMMU_ASID_SECURITY_5                             (0x9ec)
+#define MC_SMMU_ASID_SECURITY_6                             (0x9f0)
+#define MC_SMMU_ASID_SECURITY_7                             (0x9f4)
+
+#define MC_SEC_CARVEOUT_BOM                                 (0x670)
+#define MC_SEC_CARVEOUT_SIZE_MB                             (0x674)
+#define MC_SEC_CARVEOUT_REG_CTRL                            (0x678)
+
+#define MC_VIDEO_PROTECT_BOM                                (0x648)
+#define MC_VIDEO_PROTECT_SIZE_MB                            (0x64c)
+#define MC_VIDEO_PROTECT_REG_CTRL                           (0x650)
+#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0                     (0x984)
+#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1                     (0x988)
+
+#define MC_MTS_CARVEOUT_BOM                                 (0x9a0)
+#define MC_MTS_CARVEOUT_SIZE_MB                             (0x9a4)
+#define MC_MTS_CARVEOUT_ADR_HI                              (0x9a8)
+#define MC_MTS_CARVEOUT_REG_CTRL                            (0x9ac)
+
+#define MC_SECURITY_CARVEOUT1_CFG0                          (0xc08)
+#define MC_SECURITY_CARVEOUT1_BOM                           (0xc0c)
+#define MC_SECURITY_CARVEOUT1_BOM_HI                        (0xc10)
+#define MC_SECURITY_CARVEOUT1_SIZE_128KB                    (0xc14)
+#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0                (0xc18)
+#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1                (0xc1c)
+#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2                (0xc20)
+#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3                (0xc24)
+#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4                (0xc28)
+#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 (0xc2c)
+#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 (0xc30)
+#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 (0xc34)
+#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 (0xc38)
+#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 (0xc3c)
+
+#define MC_SECURITY_CARVEOUT2_CFG0                          (0xc58)
+#define MC_SECURITY_CARVEOUT2_BOM                           (0xc5c)
+#define MC_SECURITY_CARVEOUT2_BOM_HI                        (0xc60)
+#define MC_SECURITY_CARVEOUT2_SIZE_128KB                    (0xc64)
+#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0                (0xc68)
+#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1                (0xc6c)
+#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2                (0xc70)
+#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3                (0xc74)
+#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4                (0xc78)
+#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 (0xc7c)
+#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 (0xc80)
+#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 (0xc84)
+#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 (0xc88)
+#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 (0xc8c)
+
+#define MC_SECURITY_CARVEOUT3_CFG0                          (0xca8)
+#define MC_SECURITY_CARVEOUT3_BOM                           (0xcac)
+#define MC_SECURITY_CARVEOUT3_BOM_HI                        (0xcb0)
+#define MC_SECURITY_CARVEOUT3_SIZE_128KB                    (0xcb4)
+#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0                (0xcb8)
+#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1                (0xcbc)
+#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2                (0xcc0)
+#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3                (0xcc4)
+#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4                (0xcc8)
+#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 (0xccc)
+#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 (0xcd0)
+#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 (0xcd4)
+#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 (0xcd8)
+#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 (0xcdc)
+
+#define MC_SECURITY_CARVEOUT4_CFG0                          (0xcf8)
+#define MC_SECURITY_CARVEOUT4_BOM                           (0xcfc)
+#define MC_SECURITY_CARVEOUT4_BOM_HI                        (0xd00)
+#define MC_SECURITY_CARVEOUT4_SIZE_128KB                    (0xd04)
+#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0                (0xd08)
+#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1                (0xd0c)
+#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2                (0xd10)
+#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3                (0xd14)
+#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4                (0xd18)
+#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 (0xd1c)
+#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 (0xd20)
+#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 (0xd24)
+#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 (0xd28)
+#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 (0xd2c)
+
+#define MC_SECURITY_CARVEOUT5_CFG0                          (0xd48)
+#define MC_SECURITY_CARVEOUT5_BOM                           (0xd4c)
+#define MC_SECURITY_CARVEOUT5_BOM_HI                        (0xd50)
+#define MC_SECURITY_CARVEOUT5_SIZE_128KB                    (0xd54)
+#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0                (0xd58)
+#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1                (0xd5c)
+#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2                (0xd60)
+#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3                (0xd64)
+#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4                (0xd68)
+#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 (0xd6c)
+#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 (0xd70)
+#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 (0xd74)
+#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 (0xd78)
+#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 (0xd7c)
+
+
+#define MC_REG_BITS_MASK(NAME)                                      REG_NAMED_BITS_MASK    (MC, NAME)
+#define MC_REG_BITS_VALUE(NAME, VALUE)                              REG_NAMED_BITS_VALUE   (MC, NAME, VALUE)
+#define MC_REG_BITS_ENUM(NAME, ENUM)                                REG_NAMED_BITS_ENUM    (MC, NAME, ENUM)
+#define MC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(MC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
+
+#define DEFINE_MC_REG(NAME, __OFFSET__, __WIDTH__)                                                                                                                  REG_DEFINE_NAMED_REG           (MC, NAME, __OFFSET__, __WIDTH__)
+#define DEFINE_MC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE)                                                                                                         REG_DEFINE_NAMED_BIT_ENUM      (MC, NAME, __OFFSET__, ZERO, ONE)
+#define DEFINE_MC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE)                                                                                         REG_DEFINE_NAMED_TWO_BIT_ENUM  (MC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
+#define DEFINE_MC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)                                                               REG_DEFINE_NAMED_THREE_BIT_ENUM(MC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
+#define DEFINE_MC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (MC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
+
+DEFINE_MC_REG_BIT_ENUM(SMMU_CONFIG_SMMU_ENABLE, 0, DISABLE, ENABLE);
+
+DEFINE_MC_REG(SMMU_TLB_CONFIG_TLB_ACTIVE_LINES, 0, 6);
+DEFINE_MC_REG_BIT_ENUM(SMMU_TLB_CONFIG_TLB_ROUND_ROBIN_ARBITRATION, 28, DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_TLB_CONFIG_TLB_HIT_UNDER_MISS, 29, DISABLE, ENABLE);
+
+DEFINE_MC_REG(SMMU_PTC_CONFIG_PTC_INDEX_MAP,  0, 7);
+DEFINE_MC_REG(SMMU_PTC_CONFIG_PTC_REQ_LIMIT, 24, 4);
+DEFINE_MC_REG_BIT_ENUM(SMMU_PTC_CONFIG_PTC_CACHE_ENABLE, 29, DISABLE, ENABLE);
+
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_0,   0, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_1,   1, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_2,   2, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_3,   3, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_4,   4, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_5,   5, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_6,   6, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_7,   7, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_8,   8, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_9,   9, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_10, 10, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_11, 11, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_12, 12, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_13, 13, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_14, 14, NONSECURE, SECURE);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_15, 15, NONSECURE, SECURE);
+
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_0,  16, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_1,  17, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_2,  18, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_3,  19, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_4,  20, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_5,  21, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_6,  22, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_7,  23, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_8,  24, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_9,  25, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_10, 26, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_11, 27, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_12, 28, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_13, 29, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_14, 30, NONPROMOTING, PROMOTING);
+DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_15, 31, NONPROMOTING, PROMOTING);
+
+DEFINE_MC_REG(SECURITY_CFG0_SECURITY_BOM,    20, 12);
+DEFINE_MC_REG(SECURITY_CFG1_SECURITY_SIZE,    0, 13);
+DEFINE_MC_REG(SECURITY_CFG3_SECURITY_BOM_HI,  0,  2);
+
+DEFINE_MC_REG_BIT_ENUM(SEC_CARVEOUT_REG_CTRL_SEC_CARVEOUT_WRITE_ACCESS, 0, ENABLED, DISABLED);
+
+DEFINE_MC_REG_BIT_ENUM(VIDEO_PROTECT_REG_CTRL_VIDEO_PROTECT_WRITE_ACCESS,   0, ENABLED, DISABLED);
+DEFINE_MC_REG_BIT_ENUM(VIDEO_PROTECT_REG_CTRL_VIDEO_PROTECT_ALLOW_TZ_WRITE, 1, DISABLED, ENABLED);
+
+DEFINE_MC_REG_BIT_ENUM(MTS_CARVEOUT_REG_CTRL_MTS_CARVEOUT_WRITE_ACCESS, 0, ENABLED, DISABLED);
+
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_PROTECT_MODE,         0, LOCKBIT_SECURE, TZ_SECURE);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_LOCK_MODE,            1, UNLOCKED, LOCKED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_ADDRESS_TYPE,         2, ANY_ADDRESS, UNTRANSLATED_ONLY);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL0,   3, DISABLED, ENABLED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL1,   4, DISABLED, ENABLED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL2,   5, DISABLED, ENABLED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL3,   6, DISABLED, ENABLED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL0,  7, DISABLED, ENABLED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL1,  8, DISABLED, ENABLED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL2,  9, DISABLED, ENABLED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL3, 10, DISABLED, ENABLED);
+DEFINE_MC_REG(SECURITY_CARVEOUT_CFG0_APERTURE_ID, 11, 3);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL0,  14, ENABLE_CHECKS, DISABLE_CHECKS);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL1,  15, ENABLE_CHECKS, DISABLE_CHECKS);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL2,  16, ENABLE_CHECKS, DISABLE_CHECKS);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL3,  17, ENABLE_CHECKS, DISABLE_CHECKS);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL0, 18, ENABLE_CHECKS, DISABLE_CHECKS);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL1, 19, ENABLE_CHECKS, DISABLE_CHECKS);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL2, 20, ENABLE_CHECKS, DISABLE_CHECKS);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL3, 21, ENABLE_CHECKS, DISABLE_CHECKS);
+
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_SEND_CFG_TO_GPU,            22, DISABLED, ENABLED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_TZ_GLOBAL_WR_EN,            23, DISABLED, BYPASS_CHECK);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_TZ_GLOBAL_RD_EN,            24, DISABLED, BYPASS_CHECK);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_ALLOW_APERTURE_ID_MISMATCH, 25, DISABLED, ENABLED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_FORCE_APERTURE_ID_MATCH,    26, DISABLED, ENABLED);
+DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_IS_WPR,                     27, DISABLED, ENABLED);
+
+#define MC_CLIENT_ACCESS_NUM_CLIENTS   32
+
+/* _ACCESS0 */
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_PTCR,           (  0 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0A,      (  1 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0AB,     (  2 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0B,      (  3 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0BB,     (  4 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0C,      (  5 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0CB,     (  6 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_AFIR,           ( 14 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_AVPCARM7R,      ( 15 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAYHC,      ( 16 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAYHCB,     ( 17 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_HDAR,           ( 21 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_HOST1XDMAR,     ( 22 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_HOST1XR,        ( 23 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_NVENCSRD,       ( 28 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_PPCSAHBDMAR,    ( 29 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_PPCSAHBSLVR,    ( 30 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_SATAR,          ( 31 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
+
+/* _ACCESS1 */
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEBSEVR,       ( 34 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEMBER,        ( 35 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEMCER,        ( 36 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDETPER,        ( 37 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCORELPR,      ( 38 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCORER,        ( 39 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_NVENCSWR,       ( 43 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_AFIW,           ( 49 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_AVPCARM7W,      ( 50 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_HDAW,           ( 53 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_HOST1XW,        ( 54 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCORELPW,      ( 56 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCOREW,        ( 57 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_PPCSAHBDMAW,    ( 59 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_PPCSAHBSLVW,    ( 60 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_SATAW,          ( 61 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEBSEVW,       ( 62 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEDBGW,        ( 63 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
+
+/* _ACCESS2 */
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_VDEMBEW,        ( 64 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_VDETPMW,        ( 65 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPRA,          ( 68 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWA,          ( 70 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWB,          ( 71 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_HOSTR,     ( 74 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_HOSTW,     ( 75 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_DEVR,      ( 76 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_DEVW,      ( 77 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPRAB,         ( 78 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWAB,         ( 80 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWBB,         ( 81 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_TSECSRD,        ( 84 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_TSECSWR,        ( 85 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_A9AVPSCR,       ( 86 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_A9AVPSCW,       ( 87 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_GPUSRD,         ( 88 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_GPUSWR,         ( 89 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_DISPLAYT,       ( 90 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
+
+/* _ACCESS3 */
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCRA,        ( 96 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCRAA,       ( 97 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCR,         ( 98 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCRAB,       ( 99 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCWA,        (100 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCWAA,       (101 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCW,         (102 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCWAB,       (103 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_VICSRD,         (108 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_VICSWR,         (109 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_VIW,            (114 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_DISPLAYD,       (115 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVDECSRD,       (120 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVDECSWR,       (121 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_APER,           (122 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_APEW,           (123 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVJPGSRD,       (126 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVJPGSWR,       (127 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
+
+/* _ACCESS4 */
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_SESRD,          (128 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_SESWR,          (129 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_AXIAPR,         (130 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_AXIAPW,         (131 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_ETRR,           (132 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_ETRW,           (133 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_TSECRDB,        (134 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_TSECWRB,        (135 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_GPUSRD2,        (136 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
+DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_GPUSWR2,        (137 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_mselect.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_mselect.hpp
@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#define MSELECT(x) (0x50060000 + x)
+
+#define MSELECT_CONFIG   (0x000)
+
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_pmc.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_pmc.hpp
@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+#include <exosphere/reg.hpp>
+
+#define APBDEV_PMC_CNTRL             (0x000)
+#define APBDEV_PMC_DPD_SAMPLE        (0x020)
+#define APBDEV_PMC_DPD_ENABLE        (0x024)
+#define APBDEV_PMC_CLAMP_STATUS      (0x02C)
+#define APBDEV_PMC_PWRGATE_TOGGLE    (0x030)
+#define APBDEV_PMC_PWRGATE_STATUS    (0x038)
+#define APBDEV_PMC_SCRATCH0          (0x050)
+#define APBDEV_PMC_SCRATCH1          (0x054)
+#define APBDEV_PMC_SCRATCH12         (0x080)
+#define APBDEV_PMC_SCRATCH13         (0x084)
+#define APBDEV_PMC_SCRATCH18         (0x098)
+#define APBDEV_PMC_SCRATCH20         (0x0A0)
+#define APBDEV_PMC_CRYPTO_OP         (0x0F4)
+#define APBDEV_PM                    (0x014)
+#define APBDEV_PMC_WAKE2_STATUS      (0x168)
+#define APBDEV_PMC_WEAK_BIAS         (0x2C8)
+#define APBDEV_PMC_CNTRL2            (0x440)
+#define APBDEV_PMC_FUSE_CTRL         (0x450)
+#define APBDEV_PMC_IO_DPD3_REQ       (0x45C)
+#define APBDEV_PMC_IO_DPD3_STATUS    (0x460)
+#define APBDEV_PMC_IO_DPD4_REQ       (0x464)
+#define APBDEV_PMC_IO_DPD4_STATUS    (0x468)
+#define APBDEV_PMC_SET_SW_CLAMP      (0x47C)
+#define APBDEV_PMC_DDR_CNTRL         (0x4E4)
+#define APBDEV_PMC_SEC_DISABLE       (0x004)
+#define APBDEV_PMC_SEC_DISABLE2      (0x2C4)
+#define APBDEV_PMC_SEC_DISABLE3      (0x2D8)
+#define APBDEV_PMC_SEC_DISABLE4      (0x5B0)
+#define APBDEV_PMC_SEC_DISABLE5      (0x5B4)
+#define APBDEV_PMC_SEC_DISABLE6      (0x5B8)
+#define APBDEV_PMC_SEC_DISABLE7      (0x5BC)
+#define APBDEV_PMC_SEC_DISABLE8      (0x5C0)
+#define APBDEV_PMC_SCRATCH43         (0x22C)
+#define APBDEV_PMC_SCRATCH190        (0x818)
+#define APBDEV_PMC_SCRATCH200        (0x840)
+#define APBDEV_PMC_SEC_DISABLE3      (0x2D8)
+#define APBDEV_PMC_SECURE_SCRATCH4   (0x0C0)
+#define APBDEV_PMC_SECURE_SCRATCH5   (0x0C4)
+#define APBDEV_PMC_SECURE_SCRATCH6   (0x224)
+#define APBDEV_PMC_SECURE_SCRATCH7   (0x228)
+#define APBDEV_PMC_SECURE_SCRATCH16  (0x320)
+#define APBDEV_PMC_SECURE_SCRATCH21  (0x334)
+#define APBDEV_PMC_SECURE_SCRATCH24  (0x340)
+#define APBDEV_PMC_SECURE_SCRATCH25  (0x344)
+#define APBDEV_PMC_SECURE_SCRATCH26  (0x348)
+#define APBDEV_PMC_SECURE_SCRATCH27  (0x34C)
+#define APBDEV_PMC_SECURE_SCRATCH32  (0x360)
+#define APBDEV_PMC_SECURE_SCRATCH34  (0x368)
+#define APBDEV_PMC_SECURE_SCRATCH35  (0x36C)
+#define APBDEV_PMC_SECURE_SCRATCH39  (0x37C)
+#define APBDEV_PMC_SECURE_SCRATCH51  (0x3AC)
+#define APBDEV_PMC_SECURE_SCRATCH55  (0x3BC)
+#define APBDEV_PMC_SECURE_SCRATCH74  (0x408)
+#define APBDEV_PMC_SECURE_SCRATCH75  (0x40C)
+#define APBDEV_PMC_SECURE_SCRATCH76  (0x410)
+#define APBDEV_PMC_SECURE_SCRATCH77  (0x414)
+#define APBDEV_PMC_SECURE_SCRATCH78  (0x418)
+#define APBDEV_PMC_SECURE_SCRATCH99  (0xAE4)
+#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8)
+#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC)
+#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0)
+#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4)
+#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18)
+#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C)
+#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20)
+#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24)
+
+
+#define PMC_REG_BITS_MASK(NAME)                                      REG_NAMED_BITS_MASK    (APBDEV_PMC, NAME)
+#define PMC_REG_BITS_VALUE(NAME, VALUE)                              REG_NAMED_BITS_VALUE   (APBDEV_PMC, NAME, VALUE)
+#define PMC_REG_BITS_ENUM(NAME, ENUM)                                REG_NAMED_BITS_ENUM    (APBDEV_PMC, NAME, ENUM)
+#define PMC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(APBDEV_PMC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
+
+#define DEFINE_PMC_REG(NAME, __OFFSET__, __WIDTH__)                                                                                                                  REG_DEFINE_NAMED_REG           (APBDEV_PMC, NAME, __OFFSET__, __WIDTH__)
+#define DEFINE_PMC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE)                                                                                                         REG_DEFINE_NAMED_BIT_ENUM      (APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE)
+#define DEFINE_PMC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE)                                                                                         REG_DEFINE_NAMED_TWO_BIT_ENUM  (APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
+#define DEFINE_PMC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)                                                               REG_DEFINE_NAMED_THREE_BIT_ENUM(APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
+#define DEFINE_PMC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
+
+DEFINE_PMC_REG_BIT_ENUM(CNTRL_MAIN_RESET, 4, DISABLE, ENABLE)
+
+DEFINE_PMC_REG_BIT_ENUM(DPD_SAMPLE_ON, 0, DISABLE, ENABLE);
+
+DEFINE_PMC_REG_BIT_ENUM(DPD_ENABLE_ON,          0, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(DPD_ENABLE_TSC_MULT_EN, 1, DISABLE, ENABLE);
+
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CRAIL,  0, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VE,     2, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_PCX,    3, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_MPE,    6, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_SAX,    8, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE1,    9, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE2,   10, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE3,   11, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE0,   14, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_C0NC,  15, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_SOR,   17, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_DIS,   18, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_DISB,  19, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_XUSBA, 20, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_XUSBB, 21, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_XUSBC, 22, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VIC,   23, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_IRAM,  24, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_NVDEC, 25, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_NVJPG, 26, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_AUD,   27, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_DFD,   28, OFF, ON);
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VE2,   29, OFF, ON);
+
+DEFINE_PMC_REG(SET_SW_CLAMP_CRAIL, 0, 1);
+
+DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3);
+
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CRAIL,  0, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_TE,     1, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VE,     2, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_PCX,    3, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VDE,    4, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_MPE,    6, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_HEG,    7, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_SAX,    8, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE1,    9, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE2,   10, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE3,   11, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CELP,  12, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE0,   14, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_C0NC,  15, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_SOR,   17, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_C1NC,  16, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_DIS,   18, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_DISB,  19, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBA, 20, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBB, 21, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBC, 22, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VIC,   23, DISABLE, ENABLE);
+DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_IRAM,  24, DISABLE, ENABLE);
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_sb.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_sb.hpp
@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#define SB_CSR             (0x200)
+#define SB_AA64_RESET_LOW  (0x230)
+#define SB_AA64_RESET_HIGH (0x234)
+
+
+#define SB_REG_BITS_MASK(NAME)                                      REG_NAMED_BITS_MASK    (SB, NAME)
+#define SB_REG_BITS_VALUE(NAME, VALUE)                              REG_NAMED_BITS_VALUE   (SB, NAME, VALUE)
+#define SB_REG_BITS_ENUM(NAME, ENUM)                                REG_NAMED_BITS_ENUM    (SB, NAME, ENUM)
+#define SB_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(SB, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
+
+#define DEFINE_SB_REG(NAME, __OFFSET__, __WIDTH__)                                                                                                                  REG_DEFINE_NAMED_REG           (SB, NAME, __OFFSET__, __WIDTH__)
+#define DEFINE_SB_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE)                                                                                                         REG_DEFINE_NAMED_BIT_ENUM      (SB, NAME, __OFFSET__, ZERO, ONE)
+#define DEFINE_SB_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE)                                                                                         REG_DEFINE_NAMED_TWO_BIT_ENUM  (SB, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
+#define DEFINE_SB_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)                                                               REG_DEFINE_NAMED_THREE_BIT_ENUM(SB, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
+#define DEFINE_SB_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (SB, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
+
+DEFINE_SB_REG_BIT_ENUM(CSR_SECURE_BOOT_FLAG,  0, DISABLE, ENABLE);
+DEFINE_SB_REG_BIT_ENUM(CSR_NS_RST_VEC_WR_DIS, 1, ENABLE, DISABLE);
+DEFINE_SB_REG_BIT_ENUM(CSR_PIROM_DISABLE,     4, ENABLE, DISABLE);
+DEFINE_SB_REG_BIT_ENUM(CSR_HANG,              6, DISABLE, ENABLE);
+DEFINE_SB_REG_BIT_ENUM(CSR_SWDM_ENABLE,       7, DISABLE, ENABLE);
+DEFINE_SB_REG(CSR_SWDM_FAIL_COUNT,  8, 4);
+DEFINE_SB_REG(CSR_COT_FAIL_COUNT,  12, 4);
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_sysctr0.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_sysctr0.hpp
@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+#define SYSCTR0_CNTFID0  (0x020)
+#define SYSCTR0_CNTFID1  (0x024)
+
+
+#define SYSCTR0_COUNTERID4  (0xFD0)
+#define SYSCTR0_COUNTERID5  (0xFD4)
+#define SYSCTR0_COUNTERID6  (0xFD8)
+#define SYSCTR0_COUNTERID7  (0xFDC)
+#define SYSCTR0_COUNTERID0  (0xFE0)
+#define SYSCTR0_COUNTERID1  (0xFE4)
+#define SYSCTR0_COUNTERID2  (0xFE8)
+#define SYSCTR0_COUNTERID3  (0xFEC)
+#define SYSCTR0_COUNTERID8  (0xFF0)
+#define SYSCTR0_COUNTERID9  (0xFF4)
+#define SYSCTR0_COUNTERID10 (0xFF8)
+#define SYSCTR0_COUNTERID11 (0xFFC)
+
+#define SYSCTR0_COUNTERID(n) SYSCTR0_COUNTERID##n
--- a/libraries/libexosphere/include/exosphere/tegra/tegra_timer.hpp
+++ b/libraries/libexosphere/include/exosphere/tegra/tegra_timer.hpp
@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+
+#define TIMER_SHARED_TIMER_SECURE_CFG (0x1A4)
+
+#define TIMER_REG_BITS_MASK(NAME)                                      REG_NAMED_BITS_MASK    (TIMER, NAME)
+#define TIMER_REG_BITS_VALUE(NAME, VALUE)                              REG_NAMED_BITS_VALUE   (TIMER, NAME, VALUE)
+#define TIMER_REG_BITS_ENUM(NAME, ENUM)                                REG_NAMED_BITS_ENUM    (TIMER, NAME, ENUM)
+#define TIMER_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(TIMER, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
+
+#define DEFINE_TIMER_REG(NAME, __OFFSET__, __WIDTH__)                                                                                                                  REG_DEFINE_NAMED_REG           (TIMER, NAME, __OFFSET__, __WIDTH__)
+#define DEFINE_TIMER_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE)                                                                                                         REG_DEFINE_NAMED_BIT_ENUM      (TIMER, NAME, __OFFSET__, ZERO, ONE)
+#define DEFINE_TIMER_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE)                                                                                         REG_DEFINE_NAMED_TWO_BIT_ENUM  (TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
+#define DEFINE_TIMER_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)                                                               REG_DEFINE_NAMED_THREE_BIT_ENUM(TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
+#define DEFINE_TIMER_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
+
+DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR5, 5, DISABLE, ENABLE);
+DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR6, 6, DISABLE, ENABLE);
+DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR7, 7, DISABLE, ENABLE);
+DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR8, 8, DISABLE, ENABLE);
+
+DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT0, 12, DISABLE, ENABLE);
+DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT1, 13, DISABLE, ENABLE);
+DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT2, 14, DISABLE, ENABLE);
+DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT3, 15, DISABLE, ENABLE);
--- a/libraries/libexosphere/include/exosphere/tsec.hpp
+++ b/libraries/libexosphere/include/exosphere/tsec.hpp
@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::tsec {
+
+    void Lock();
+
+}
--- a/libraries/libexosphere/include/exosphere/uart.hpp
+++ b/libraries/libexosphere/include/exosphere/uart.hpp
@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::uart {
+
+    enum Port {
+        Port_A = 0,
+        Port_B = 1,
+        Port_C = 2,
+
+        Port_Count = 3,
+
+        Port_ReservedDebug = Port_A,
+        Port_RightJoyCon   = Port_B,
+        Port_LeftJoyCon    = Port_C,
+    };
+
+    enum Flags {
+        Flag_None     = (0u << 0),
+        Flag_Inverted = (1u << 0),
+    };
+
+    void SetRegisterAddress(uintptr_t address);
+
+    void Initialize(Port port, int baud_rate, u32 flags);
+
+}
--- a/libraries/libexosphere/include/exosphere/util.hpp
+++ b/libraries/libexosphere/include/exosphere/util.hpp
@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::util {
+
+    void SetRegisterAddress(uintptr_t address);
+
+    u32 GetMicroSeconds();
+    void WaitMicroSeconds(int us);
+
+    void ClearMemory(void *ptr, size_t size);
+
+    template<typename T, typename U> requires std::integral<T> && std::integral<U>
+    constexpr T DivideUp(T x, U y) {
+        return (x + (y - 1)) / y;
+    }
+
+}
--- a/libraries/libexosphere/include/exosphere/wdt.hpp
+++ b/libraries/libexosphere/include/exosphere/wdt.hpp
@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <vapours.hpp>
+
+namespace ams::wdt {
+
+    void SetRegisterAddress(uintptr_t address);
+    void Reboot();
+
+}