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emummc: temp delete
This commit is contained in:
Michael Scire
parent
b1a4a0db67
commit
e3cb5e74b9
112 changed files with 0 additions and 21966 deletions
340
emummc/source/power/max77620.h
vendored
340
emummc/source/power/max77620.h
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/*
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* Defining registers address and its bit definitions of MAX77620 and MAX20024
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*
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* Copyright (c) 2016 NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#ifndef _MFD_MAX77620_H_
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#define _MFD_MAX77620_H_
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#define MAX77620_I2C_ADDR 0x3C
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/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
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#define MAX77620_REG_CNFGGLBL1 0x00
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#define MAX77620_CNFGGLBL1_LBDAC_EN (1 << 7)
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#define MAX77620_CNFGGLBL1_MPPLD (1 << 6)
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#define MAX77620_CNFGGLBL1_LBHYST ((1 << 5) | (1 << 4))
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#define MAX77620_CNFGGLBL1_LBHYST_100 (0 << 4)
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#define MAX77620_CNFGGLBL1_LBHYST_200 (1 << 4)
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#define MAX77620_CNFGGLBL1_LBHYST_300 (2 << 4)
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#define MAX77620_CNFGGLBL1_LBHYST_400 (3 << 4)
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#define MAX77620_CNFGGLBL1_LBDAC_MASK 0x0E
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#define MAX77620_CNFGGLBL1_LBDAC_2700 (0 << 1)
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#define MAX77620_CNFGGLBL1_LBDAC_2800 (1 << 1)
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#define MAX77620_CNFGGLBL1_LBDAC_2900 (2 << 1)
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#define MAX77620_CNFGGLBL1_LBDAC_3000 (3 << 1)
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#define MAX77620_CNFGGLBL1_LBDAC_3100 (4 << 1)
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#define MAX77620_CNFGGLBL1_LBDAC_3200 (5 << 1)
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#define MAX77620_CNFGGLBL1_LBDAC_3300 (6 << 1)
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#define MAX77620_CNFGGLBL1_LBDAC_3400 (7 << 1)
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#define MAX77620_CNFGGLBL1_LBRSTEN (1 << 0)
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#define MAX77620_REG_CNFGGLBL2 0x01
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#define MAX77620_REG_CNFGGLBL3 0x02
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#define MAX77620_WDTC_MASK 0x3
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#define MAX77620_WDTOFFC (1 << 4)
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#define MAX77620_WDTSLPC (1 << 3)
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#define MAX77620_WDTEN (1 << 2)
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#define MAX77620_TWD_MASK 0x3
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#define MAX77620_TWD_2s 0x0
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#define MAX77620_TWD_16s 0x1
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#define MAX77620_TWD_64s 0x2
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#define MAX77620_TWD_128s 0x3
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#define MAX77620_REG_CNFG1_32K 0x03
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#define MAX77620_CNFG1_32K_OUT0_EN (1 << 2)
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#define MAX77620_REG_CNFGBBC 0x04
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#define MAX77620_CNFGBBC_ENABLE (1 << 0)
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#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
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#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
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#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
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#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
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#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5)
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#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
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#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
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#define MAX77620_CNFGBBC_RESISTOR_100 (0 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
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#define MAX77620_CNFGBBC_RESISTOR_1K (1 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
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#define MAX77620_CNFGBBC_RESISTOR_3K (2 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
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#define MAX77620_CNFGBBC_RESISTOR_6K (3 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
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#define MAX77620_REG_IRQTOP 0x05
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#define MAX77620_IRQ_TOP_GLBL_MASK (1 << 7)
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#define MAX77620_IRQ_TOP_SD_MASK (1 << 6)
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#define MAX77620_IRQ_TOP_LDO_MASK (1 << 5)
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#define MAX77620_IRQ_TOP_GPIO_MASK (1 << 4)
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#define MAX77620_IRQ_TOP_RTC_MASK (1 << 3)
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#define MAX77620_IRQ_TOP_32K_MASK (1 << 2)
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#define MAX77620_IRQ_TOP_ONOFF_MASK (1 << 1)
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#define MAX77620_REG_INTLBT 0x06
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#define MAX77620_REG_IRQTOPM 0x0D
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#define MAX77620_IRQ_LBM_MASK (1 << 3)
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#define MAX77620_IRQ_TJALRM1_MASK (1 << 2)
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#define MAX77620_IRQ_TJALRM2_MASK (1 << 1)
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#define MAX77620_REG_IRQSD 0x07
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#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
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#define MAX77620_REG_IRQ_LVL2_L8 0x09
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#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
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#define MAX77620_REG_ONOFFIRQ 0x0B
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#define MAX77620_REG_NVERC 0x0C
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#define MAX77620_REG_INTENLBT 0x0E
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#define MAX77620_GLBLM_MASK (1 << 0)
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#define MAX77620_REG_IRQMASKSD 0x0F
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#define MAX77620_REG_IRQ_MSK_L0_7 0x10
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#define MAX77620_REG_IRQ_MSK_L8 0x11
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#define MAX77620_REG_ONOFFIRQM 0x12
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#define MAX77620_REG_STATLBT 0x13
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#define MAX77620_REG_STATSD 0x14
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#define MAX77620_REG_ONOFFSTAT 0x15
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/* SD and LDO Registers */
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#define MAX77620_REG_SD0 0x16
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#define MAX77620_REG_SD1 0x17
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#define MAX77620_REG_SD2 0x18
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#define MAX77620_REG_SD3 0x19
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#define MAX77620_REG_SD4 0x1A
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#define MAX77620_SDX_VOLT_MASK 0xFF
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#define MAX77620_SD0_VOLT_MASK 0x3F
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#define MAX77620_SD1_VOLT_MASK 0x7F
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#define MAX77620_LDO_VOLT_MASK 0x3F
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#define MAX77620_REG_DVSSD0 0x1B
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#define MAX77620_REG_DVSSD1 0x1C
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#define MAX77620_REG_SD0_CFG 0x1D
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#define MAX77620_REG_SD1_CFG 0x1E
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#define MAX77620_REG_SD2_CFG 0x1F
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#define MAX77620_REG_SD3_CFG 0x20
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#define MAX77620_REG_SD4_CFG 0x21
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#define MAX77620_REG_SD_CFG2 0x22
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#define MAX77620_REG_LDO0_CFG 0x23
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#define MAX77620_REG_LDO0_CFG2 0x24
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#define MAX77620_REG_LDO1_CFG 0x25
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#define MAX77620_REG_LDO1_CFG2 0x26
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#define MAX77620_REG_LDO2_CFG 0x27
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#define MAX77620_REG_LDO2_CFG2 0x28
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#define MAX77620_REG_LDO3_CFG 0x29
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#define MAX77620_REG_LDO3_CFG2 0x2A
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#define MAX77620_REG_LDO4_CFG 0x2B
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#define MAX77620_REG_LDO4_CFG2 0x2C
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#define MAX77620_REG_LDO5_CFG 0x2D
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#define MAX77620_REG_LDO5_CFG2 0x2E
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#define MAX77620_REG_LDO6_CFG 0x2F
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#define MAX77620_REG_LDO6_CFG2 0x30
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#define MAX77620_REG_LDO7_CFG 0x31
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#define MAX77620_REG_LDO7_CFG2 0x32
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#define MAX77620_REG_LDO8_CFG 0x33
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#define MAX77620_REG_LDO8_CFG2 0x34
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#define MAX77620_LDO_POWER_MODE_MASK 0xC0
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#define MAX77620_LDO_POWER_MODE_SHIFT 6
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#define MAX77620_POWER_MODE_NORMAL 3
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#define MAX77620_POWER_MODE_LPM 2
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#define MAX77620_POWER_MODE_GLPM 1
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#define MAX77620_POWER_MODE_DISABLE 0
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#define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2)
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#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1)
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#define MAX77620_LDO_CFG2_ADE_DISABLE (0 << 1)
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#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1)
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#define MAX77620_LDO_CFG2_SS_MASK (1 << 0)
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#define MAX77620_LDO_CFG2_SS_FAST (1 << 0)
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#define MAX77620_LDO_CFG2_SS_SLOW 0
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#define MAX77620_REG_LDO_CFG3 0x35
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#define MAX77620_TRACK4_MASK (1 << 5)
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#define MAX77620_TRACK4_SHIFT 5
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#define MAX77620_LDO_SLEW_RATE_MASK 0x1
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#define MAX77620_REG_GPIO0 0x36
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#define MAX77620_REG_GPIO1 0x37
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#define MAX77620_REG_GPIO2 0x38
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#define MAX77620_REG_GPIO3 0x39
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#define MAX77620_REG_GPIO4 0x3A
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#define MAX77620_REG_GPIO5 0x3B
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#define MAX77620_REG_GPIO6 0x3C
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#define MAX77620_REG_GPIO7 0x3D
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#define MAX77620_REG_PUE_GPIO 0x3E
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#define MAX77620_REG_PDE_GPIO 0x3F
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#define MAX77620_REG_AME_GPIO 0x40
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#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0)
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#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0)
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#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN (0 << 0)
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#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1)
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#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1)
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#define MAX77620_CNFG_GPIO_DIR_OUTPUT (0 << 1)
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#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2)
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#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3)
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#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3)
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#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW (0 << 3)
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#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
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#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4)
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#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5)
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#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
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#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
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#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
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#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
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#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
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#define MAX77620_REG_ONOFFCNFG1 0x41
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#define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7)
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#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
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#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
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#define MAX77620_ONOFFCNFG1_SLPEN (1 << 2)
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#define MAX77620_ONOFFCNFG1_PWR_OFF (1 << 1)
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#define MAX20024_ONOFFCNFG1_CLRSE 0x18
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#define MAX77620_REG_ONOFFCNFG2 0x42
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#define MAX77620_ONOFFCNFG2_SFT_RST_WK (1 << 7)
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#define MAX77620_ONOFFCNFG2_WD_RST_WK (1 << 6)
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#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK (1 << 5)
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#define MAX77620_ONOFFCNFG2_WK_ALARM1 (1 << 2)
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#define MAX77620_ONOFFCNFG2_WK_EN0 (1 << 0)
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/* FPS Registers */
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#define MAX77620_REG_FPS_CFG0 0x43
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#define MAX77620_REG_FPS_CFG1 0x44
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#define MAX77620_REG_FPS_CFG2 0x45
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#define MAX77620_REG_FPS_LDO0 0x46
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#define MAX77620_REG_FPS_LDO1 0x47
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#define MAX77620_REG_FPS_LDO2 0x48
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#define MAX77620_REG_FPS_LDO3 0x49
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#define MAX77620_REG_FPS_LDO4 0x4A
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#define MAX77620_REG_FPS_LDO5 0x4B
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#define MAX77620_REG_FPS_LDO6 0x4C
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#define MAX77620_REG_FPS_LDO7 0x4D
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#define MAX77620_REG_FPS_LDO8 0x4E
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#define MAX77620_REG_FPS_SD0 0x4F
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#define MAX77620_REG_FPS_SD1 0x50
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#define MAX77620_REG_FPS_SD2 0x51
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#define MAX77620_REG_FPS_SD3 0x52
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#define MAX77620_REG_FPS_SD4 0x53
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#define MAX77620_REG_FPS_NONE 0
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#define MAX77620_FPS_SRC_MASK 0xC0
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#define MAX77620_FPS_SRC_SHIFT 6
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#define MAX77620_FPS_PU_PERIOD_MASK 0x38
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#define MAX77620_FPS_PU_PERIOD_SHIFT 3
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#define MAX77620_FPS_PD_PERIOD_MASK 0x07
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#define MAX77620_FPS_PD_PERIOD_SHIFT 0
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/* Minimum and maximum FPS period time (in microseconds) are
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* different for MAX77620 and Max20024.
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*/
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#define MAX77620_FPS_COUNT 3
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#define MAX77620_FPS_PERIOD_MIN_US 40
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#define MAX20024_FPS_PERIOD_MIN_US 20
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#define MAX77620_FPS_PERIOD_MAX_US 2560
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#define MAX20024_FPS_PERIOD_MAX_US 5120
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#define MAX77620_REG_FPS_GPIO1 0x54
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#define MAX77620_REG_FPS_GPIO2 0x55
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#define MAX77620_REG_FPS_GPIO3 0x56
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#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
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#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
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#define MAX77620_FPS_EN_SRC_MASK 0x06
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#define MAX77620_FPS_EN_SRC_SHIFT 1
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#define MAX77620_FPS_ENFPS_SW_MASK 0x01
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#define MAX77620_FPS_ENFPS_SW 0x01
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#define MAX77620_REG_FPS_RSO 0x57
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#define MAX77620_REG_CID0 0x58
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#define MAX77620_REG_CID1 0x59
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#define MAX77620_REG_CID2 0x5A
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#define MAX77620_REG_CID3 0x5B
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#define MAX77620_REG_CID4 0x5C
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#define MAX77620_REG_CID5 0x5D
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#define MAX77620_REG_DVSSD4 0x5E
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#define MAX20024_REG_MAX_ADD 0x70
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#define MAX77620_CID_DIDM_MASK 0xF0
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#define MAX77620_CID_DIDM_SHIFT 4
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/* CNCG2SD */
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#define MAX77620_SD_CNF2_ROVS_EN_SD1 (1 << 1)
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#define MAX77620_SD_CNF2_ROVS_EN_SD0 (1 << 2)
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/* Device Identification Metal */
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#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
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/* Device Indentification OTP */
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#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
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/* SD CNFG1 */
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#define MAX77620_SD_SR_MASK 0xC0
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#define MAX77620_SD_SR_SHIFT 6
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#define MAX77620_SD_POWER_MODE_MASK 0x30
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#define MAX77620_SD_POWER_MODE_SHIFT 4
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#define MAX77620_SD_CFG1_ADE_MASK (1 << 3)
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#define MAX77620_SD_CFG1_ADE_DISABLE 0
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#define MAX77620_SD_CFG1_ADE_ENABLE (1 << 3)
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#define MAX77620_SD_FPWM_MASK 0x04
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#define MAX77620_SD_FPWM_SHIFT 2
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#define MAX77620_SD_FSRADE_MASK 0x01
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#define MAX77620_SD_FSRADE_SHIFT 0
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#define MAX77620_SD_CFG1_FPWM_SD_MASK (1 << 2)
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#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
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#define MAX77620_SD_CFG1_FPWM_SD_FPWM (1 << 2)
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#define MAX20024_SD_CFG1_MPOK_MASK (1 << 1)
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#define MAX77620_SD_CFG1_FSRADE_SD_MASK (1 << 0)
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#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
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#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE3 (1 << 3)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE4 (1 << 4)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE5 (1 << 5)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE6 (1 << 6)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE7 (1 << 7)
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/* Interrupts */
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enum {
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MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
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MAX77620_IRQ_TOP_SD, /* SD power fail */
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MAX77620_IRQ_TOP_LDO, /* LDO power fail */
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MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
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MAX77620_IRQ_TOP_RTC, /* RTC */
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MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
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MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
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MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
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MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
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MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
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};
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/* GPIOs */
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enum {
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MAX77620_GPIO0,
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MAX77620_GPIO1,
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MAX77620_GPIO2,
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MAX77620_GPIO3,
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MAX77620_GPIO4,
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MAX77620_GPIO5,
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MAX77620_GPIO6,
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MAX77620_GPIO7,
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MAX77620_GPIO_NR,
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};
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/* FPS Source */
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enum max77620_fps_src {
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MAX77620_FPS_SRC_0,
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MAX77620_FPS_SRC_1,
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MAX77620_FPS_SRC_2,
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MAX77620_FPS_SRC_NONE,
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MAX77620_FPS_SRC_DEF,
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};
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enum max77620_chip_id {
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MAX77620,
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MAX20024,
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};
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||||
|
||||
#endif /* _MFD_MAX77620_H_ */
|
||||
159
emummc/source/power/max7762x.c
vendored
159
emummc/source/power/max7762x.c
vendored
|
|
@ -1,159 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2019 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "max7762x.h"
|
||||
#include "max77620.h"
|
||||
#include "../soc/i2c.h"
|
||||
#include "../utils/util.h"
|
||||
|
||||
#define REGULATOR_SD 0
|
||||
#define REGULATOR_LDO 1
|
||||
|
||||
typedef struct _max77620_regulator_t
|
||||
{
|
||||
u8 type;
|
||||
const char *name;
|
||||
u8 reg_sd;
|
||||
|
||||
u32 mv_step;
|
||||
u32 mv_min;
|
||||
u32 mv_default;
|
||||
u32 mv_max;
|
||||
|
||||
u8 volt_addr;
|
||||
u8 cfg_addr;
|
||||
|
||||
u8 volt_mask;
|
||||
u8 enable_mask;
|
||||
u8 enable_shift;
|
||||
u8 status_mask;
|
||||
|
||||
u8 fps_addr;
|
||||
u8 fps_src;
|
||||
u8 pd_period;
|
||||
u8 pu_period;
|
||||
} max77620_regulator_t;
|
||||
|
||||
static const max77620_regulator_t _pmic_regulators[] = {
|
||||
{ REGULATOR_SD, "sd0", 0x16, 12500, 600000, 625000, 1400000, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, MAX77620_SD0_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x80, MAX77620_REG_FPS_SD0, 1, 7, 1 },
|
||||
{ REGULATOR_SD, "sd1", 0x17, 12500, 600000, 1125000, 1125000, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x40, MAX77620_REG_FPS_SD1, 0, 1, 5 },
|
||||
{ REGULATOR_SD, "sd2", 0x18, 12500, 600000, 1325000, 1350000, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, MAX77620_SDX_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x20, MAX77620_REG_FPS_SD2, 1, 5, 2 },
|
||||
{ REGULATOR_SD, "sd3", 0x19, 12500, 600000, 1800000, 1800000, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, MAX77620_SDX_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x10, MAX77620_REG_FPS_SD3, 0, 3, 3 },
|
||||
{ REGULATOR_LDO, "ldo0", 0x00, 25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO0, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo1", 0x00, 25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO1, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo2", 0x00, 50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO2, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo3", 0x00, 50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO3, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo4", 0x00, 12500, 800000, 850000, 850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO4, 0, 7, 1 },
|
||||
{ REGULATOR_LDO, "ldo5", 0x00, 50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO5, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo6", 0x00, 50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO6, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo7", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO7, 1, 4, 3 },
|
||||
{ REGULATOR_LDO, "ldo8", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO8, 3, 7, 0 }
|
||||
};
|
||||
|
||||
int max77620_regulator_get_status(u32 id)
|
||||
{
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
if (reg->type == REGULATOR_SD)
|
||||
return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_STATSD) & reg->status_mask) ? 0 : 1;
|
||||
return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->cfg_addr) & 8) ? 1 : 0;
|
||||
}
|
||||
|
||||
int max77620_regulator_config_fps(u32 id)
|
||||
{
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg->fps_addr,
|
||||
(reg->fps_src << MAX77620_FPS_SRC_SHIFT) | (reg->pu_period << MAX77620_FPS_PU_PERIOD_SHIFT) | (reg->pd_period));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int max77620_regulator_set_voltage(u32 id, u32 mv)
|
||||
{
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
if (mv < reg->mv_min || mv > reg->mv_max)
|
||||
return 0;
|
||||
|
||||
u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
|
||||
u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr);
|
||||
val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr, val);
|
||||
usleep(1000);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int max77620_regulator_enable(u32 id, int enable)
|
||||
{
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
u32 addr = reg->type == REGULATOR_SD ? reg->cfg_addr : reg->volt_addr;
|
||||
u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, addr);
|
||||
if (enable)
|
||||
val = (val & ~reg->enable_mask) | ((MAX77620_POWER_MODE_NORMAL << reg->enable_shift) & reg->enable_mask);
|
||||
else
|
||||
val &= ~reg->enable_mask;
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, addr, val);
|
||||
usleep(1000);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int max77620_regulator_set_volt_and_flags(u32 id, u32 mv, u8 flags)
|
||||
{
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
if (mv < reg->mv_min || mv > reg->mv_max)
|
||||
return 0;
|
||||
|
||||
u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
|
||||
u8 val = ((flags << reg->enable_shift) & ~reg->volt_mask) | (mult & reg->volt_mask);
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr, val);
|
||||
usleep(1000);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void max77620_config_default()
|
||||
{
|
||||
for (u32 i = 1; i <= REGULATOR_MAX; i++)
|
||||
{
|
||||
i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4);
|
||||
max77620_regulator_config_fps(i);
|
||||
max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default);
|
||||
if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE)
|
||||
max77620_regulator_enable(i, 1);
|
||||
}
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, 4);
|
||||
}
|
||||
117
emummc/source/power/max7762x.h
vendored
117
emummc/source/power/max7762x.h
vendored
|
|
@ -1,117 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2019 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _MAX7762X_H_
|
||||
#define _MAX7762X_H_
|
||||
|
||||
#include "../utils/types.h"
|
||||
|
||||
/*
|
||||
* Switch Power domains (max77620):
|
||||
* Name | Usage | uV step | uV min | uV default | uV max | Init
|
||||
*-------+---------------+---------+--------+------------+---------+------------------
|
||||
* sd0 | SoC | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1)
|
||||
* sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1)
|
||||
* sd2 | ldo{0-1, 7-8} | 12500 | 600000 | 1325000 | 1350000 | 1.325V (pcv)
|
||||
* sd3 | 1.8V general | 12500 | 600000 | 1800000 | 1800000 |
|
||||
* ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1)
|
||||
* ldo1 | XUSB, PCIE | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv)
|
||||
* ldo2 | SDMMC1 | 50000 | 800000 | 1800000 | 3300000 |
|
||||
* ldo3 | GC ASIC | 50000 | 800000 | 3100000 | 3100000 | 3.1V (pcv)
|
||||
* ldo4 | RTC | 12500 | 800000 | 850000 | 850000 |
|
||||
* ldo5 | GC ASIC | 50000 | 800000 | 1800000 | 1800000 | 1.8V (pcv)
|
||||
* ldo6 | Touch, ALS | 50000 | 800000 | 2900000 | 2900000 | 2.9V
|
||||
* ldo7 | XUSB | 50000 | 800000 | 1050000 | 1050000 |
|
||||
* ldo8 | XUSB, DC | 50000 | 800000 | 1050000 | 1050000 |
|
||||
*/
|
||||
|
||||
/*
|
||||
* MAX77620_AME_GPIO: control GPIO modes (bits 0 - 7 correspond to GPIO0 - GPIO7); 0 -> GPIO, 1 -> alt-mode
|
||||
* MAX77620_REG_GPIOx: 0x9 sets output and enable
|
||||
*/
|
||||
|
||||
/*! MAX77620 partitions. */
|
||||
#define REGULATOR_SD0 0
|
||||
#define REGULATOR_SD1 1
|
||||
#define REGULATOR_SD2 2
|
||||
#define REGULATOR_SD3 3
|
||||
#define REGULATOR_LDO0 4
|
||||
#define REGULATOR_LDO1 5
|
||||
#define REGULATOR_LDO2 6
|
||||
#define REGULATOR_LDO3 7
|
||||
#define REGULATOR_LDO4 8
|
||||
#define REGULATOR_LDO5 9
|
||||
#define REGULATOR_LDO6 10
|
||||
#define REGULATOR_LDO7 11
|
||||
#define REGULATOR_LDO8 12
|
||||
#define REGULATOR_MAX 12
|
||||
|
||||
#define MAX77621_CPU_I2C_ADDR 0x1B
|
||||
#define MAX77621_GPU_I2C_ADDR 0x1C
|
||||
|
||||
#define MAX77621_VOUT_REG 0
|
||||
#define MAX77621_VOUT_DVC_REG 1
|
||||
#define MAX77621_CONTROL1_REG 2
|
||||
#define MAX77621_CONTROL2_REG 3
|
||||
|
||||
/* MAX77621_VOUT */
|
||||
#define MAX77621_VOUT_ENABLE (1 << 7)
|
||||
#define MAX77621_VOUT_MASK 0x7F
|
||||
#define MAX77621_VOUT_0_95V 0x37
|
||||
#define MAX77621_VOUT_1_09V 0x4F
|
||||
|
||||
/* MAX77621_VOUT_DVC_DVS */
|
||||
#define MAX77621_DVS_VOUT_MASK 0x7F
|
||||
|
||||
/* MAX77621_CONTROL1 */
|
||||
#define MAX77621_SNS_ENABLE (1 << 7)
|
||||
#define MAX77621_FPWM_EN_M (1 << 6)
|
||||
#define MAX77621_NFSR_ENABLE (1 << 5)
|
||||
#define MAX77621_AD_ENABLE (1 << 4)
|
||||
#define MAX77621_BIAS_ENABLE (1 << 3)
|
||||
#define MAX77621_FREQSHIFT_9PER (1 << 2)
|
||||
|
||||
#define MAX77621_RAMP_12mV_PER_US 0x0
|
||||
#define MAX77621_RAMP_25mV_PER_US 0x1
|
||||
#define MAX77621_RAMP_50mV_PER_US 0x2
|
||||
#define MAX77621_RAMP_200mV_PER_US 0x3
|
||||
#define MAX77621_RAMP_MASK 0x3
|
||||
|
||||
/* MAX77621_CONTROL2 */
|
||||
#define MAX77621_WDTMR_ENABLE (1 << 6)
|
||||
#define MAX77621_DISCH_ENBABLE (1 << 5)
|
||||
#define MAX77621_FT_ENABLE (1 << 4)
|
||||
#define MAX77621_T_JUNCTION_120 (1 << 7)
|
||||
|
||||
#define MAX77621_CKKADV_TRIP_DISABLE 0xC
|
||||
#define MAX77621_CKKADV_TRIP_75mV_PER_US 0x0
|
||||
#define MAX77621_CKKADV_TRIP_150mV_PER_US 0x4
|
||||
#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS 0x8
|
||||
|
||||
#define MAX77621_INDUCTOR_MIN_30_PER 0x0
|
||||
#define MAX77621_INDUCTOR_NOMINAL 0x1
|
||||
#define MAX77621_INDUCTOR_PLUS_30_PER 0x2
|
||||
#define MAX77621_INDUCTOR_PLUS_60_PER 0x3
|
||||
|
||||
int max77620_regulator_get_status(u32 id);
|
||||
int max77620_regulator_config_fps(u32 id);
|
||||
int max77620_regulator_set_voltage(u32 id, u32 mv);
|
||||
int max77620_regulator_enable(u32 id, int enable);
|
||||
int max77620_regulator_set_volt_and_flags(u32 id, u32 mv, u8 flags);
|
||||
void max77620_config_default();
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue