mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-05-19 17:35:06 -04:00
exo2: Implement the rest of main/return-to-el1
This commit is contained in:
Michael Scire
SciresM
parent
87bdc46beb
commit
dc6abf9f68
19 changed files with 801 additions and 93 deletions
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@ -18,6 +18,7 @@
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#include "secmon_error.hpp"
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#include "secmon_cpu_context.hpp"
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#include "secmon_interrupt_handler.hpp"
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#include "secmon_misc.hpp"
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namespace ams::secmon {
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@ -28,6 +29,8 @@ namespace ams::secmon {
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constexpr inline const uintptr_t FLOW_CTLR = secmon::MemoryRegionVirtualDeviceFlowController.GetAddress();
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constexpr inline const uintptr_t PMC = secmon::MemoryRegionVirtualDevicePmc.GetAddress();
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constexpr inline const uintptr_t MC = secmon::MemoryRegionVirtualDeviceMemoryController.GetAddress();
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constexpr inline const uintptr_t EVP = secmon::MemoryRegionVirtualDeviceExceptionVectors.GetAddress();
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constexpr inline const uintptr_t CLK_RST = secmon::MemoryRegionVirtualDeviceClkRst.GetAddress();
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alignas(8) constinit u8 g_se_aes_key_slot_test_vector[se::AesBlockSize] = {};
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@ -621,7 +624,7 @@ namespace ams::secmon {
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reg::Read (MC + MC_SMMU_TLB_CONFIG);
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/* Flush the entire translation lookaside buffer, and read TLB_CONFIG to ensure the flush takes. */
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reg::Write(MC + MC_SMMU_PTC_FLUSH, 0);
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reg::Write(MC + MC_SMMU_TLB_FLUSH, 0);
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reg::Read (MC + MC_SMMU_TLB_CONFIG);
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/* Enable the SMMU, and read TLB_CONFIG to ensure the enable takes. */
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@ -722,6 +725,173 @@ namespace ams::secmon {
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hw::InstructionSynchronizationBarrier();
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}
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void SetupGpuCarveout() {
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/* Configure carveout 2. */
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reg::Write(MC + MC_SECURITY_CARVEOUT2_BOM, static_cast<u32>(MemoryRegionDramGpuCarveout.GetAddress() >> 0));
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reg::Write(MC + MC_SECURITY_CARVEOUT2_BOM_HI, static_cast<u32>(MemoryRegionDramGpuCarveout.GetAddress() >> BITSIZEOF(u32)));
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reg::Write(MC + MC_SECURITY_CARVEOUT2_SIZE_128KB, MemoryRegionDramGpuCarveout.GetSize() / 128_KB);
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0, 0);
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1, 0);
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2, MC_REG_BITS_ENUM (CLIENT_ACCESS2_GPUSRD, ENABLE),
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MC_REG_BITS_ENUM (CLIENT_ACCESS2_GPUSWR, ENABLE),
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MC_REG_BITS_ENUM (CLIENT_ACCESS2_TSECSRD, ENABLE));
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3, 0);
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4, MC_REG_BITS_ENUM (CLIENT_ACCESS4_GPUSRD2, ENABLE),
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MC_REG_BITS_ENUM (CLIENT_ACCESS4_GPUSWR2, ENABLE));
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0, 0);
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1, 0);
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2, 0);
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3, 0);
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4, 0);
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reg::Write(MC + MC_SECURITY_CARVEOUT2_CFG0, MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_IS_WPR, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_FORCE_APERTURE_ID_MATCH, ENABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_ALLOW_APERTURE_ID_MISMATCH, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_TZ_GLOBAL_RD_EN, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_TZ_GLOBAL_WR_EN, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_SEND_CFG_TO_GPU, ENABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL3, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL2, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL1, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL0, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL3, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL2, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL1, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL0, ENABLE_CHECKS),
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MC_REG_BITS_VALUE(SECURITY_CARVEOUT_CFG0_APERTURE_ID, 2),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL3, ENABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL2, ENABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL1, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL0, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL3, ENABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL2, ENABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL1, ENABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL0, ENABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_ADDRESS_TYPE, UNTRANSLATED_ONLY),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_LOCK_MODE, LOCKED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_PROTECT_MODE, LOCKBIT_SECURE));
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}
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void DisableArc() {
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/* Configure IRAM top/bottom to point to memory ends (disabling redirection). */
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reg::Write(MC + MC_IRAM_BOM, (~0u) & MC_IRAM_BOM_WRITE_MASK);
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reg::Write(MC + MC_IRAM_TOM, ( 0u) & MC_IRAM_TOM_WRITE_MASK);
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/* Lock the IRAM aperture. */
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reg::Write(MC + MC_IRAM_REG_CTRL, MC_REG_BITS_ENUM(IRAM_REG_CTRL_IRAM_CFG_WRITE_ACCESS, DISABLED));
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/* Disable the ARC clock gate override. */
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reg::ReadWrite(CLK_RST + CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD, CLK_RST_REG_BITS_ENUM(LVL2_CLK_GATE_OVRD_ARC_CLK_OVR_ON, OFF));
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/* Rea IRAM REG CTRL to make sure our writes take. */
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reg::Read(MC + MC_IRAM_REG_CTRL);
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}
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void FinalizeCarveoutSecureScratchRegisters() {
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/* Define carveout scratch values. */
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constexpr uintptr_t WarmbootCarveoutAddress = MemoryRegionDram.GetAddress();
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constexpr size_t WarmbootCarveoutSize = 128_KB;
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#define MC_ENABLE_CLIENT_ACCESS(INDEX, WHICH) MC_REG_BITS_ENUM(CLIENT_ACCESS##INDEX##_##WHICH, ENABLE)
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constexpr u32 WarmbootCarveoutClientAccess0 = reg::Encode(MC_ENABLE_CLIENT_ACCESS(0, AVPCARM7R),
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MC_ENABLE_CLIENT_ACCESS(0, PPCSAHBSLVR));
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constexpr u32 WarmbootCarveoutClientAccess1 = reg::Encode(MC_ENABLE_CLIENT_ACCESS(1, AVPCARM7W));
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#undef MC_ENABLE_CLIENT_ACCESS
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constexpr u32 WarmbootCarveoutForceInternalAccess0 = reg::Encode(MC_REG_BITS_ENUM(CLIENT_ACCESS0_AVPCARM7R, ENABLE),
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MC_REG_BITS_ENUM(CLIENT_ACCESS0_PPCSAHBSLVR, ENABLE));
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constexpr u32 WarmbootCarveoutForceInternalAccess1 = reg::Encode(MC_REG_BITS_ENUM(CLIENT_ACCESS1_AVPCARM7W, ENABLE));
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constexpr u32 WarmbootCarveoutConfig = reg::Encode(MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_IS_WPR, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_FORCE_APERTURE_ID_MATCH, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_ALLOW_APERTURE_ID_MISMATCH, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_TZ_GLOBAL_RD_EN, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_TZ_GLOBAL_WR_EN, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_SEND_CFG_TO_GPU, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL3, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL2, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL1, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL0, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL3, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL2, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL1, ENABLE_CHECKS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL0, ENABLE_CHECKS),
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MC_REG_BITS_VALUE(SECURITY_CARVEOUT_CFG0_APERTURE_ID, 0),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL3, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL2, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL1, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL0, ENABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL3, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL2, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL1, DISABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL0, ENABLED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_ADDRESS_TYPE, ANY_ADDRESS),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_LOCK_MODE, UNLOCKED),
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MC_REG_BITS_ENUM (SECURITY_CARVEOUT_CFG0_PROTECT_MODE, LOCKBIT_SECURE));
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/* Save the carveout values into secure scratch. */
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/* Save MC_SECURITY_CARVEOUT4_BOM. */
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reg::ReadWrite(PMC + APBDEV_PMC_SECURE_SCRATCH51, REG_BITS_VALUE( 0, 15, WarmbootCarveoutAddress >> 17));
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/* Save MC_SECURITY_CARVEOUT4_BOM_HI. */
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reg::ReadWrite(PMC + APBDEV_PMC_SECURE_SCRATCH16, REG_BITS_VALUE(30, 2, WarmbootCarveoutAddress >> 32));
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/* Save MC_SECURITY_CARVEOUT4_SIZE_128KB. */
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reg::ReadWrite(PMC + APBDEV_PMC_SECURE_SCRATCH55, REG_BITS_VALUE(12, 12, WarmbootCarveoutSize / 128_KB));
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/* Save MC_SECURITY_CARVEOUT4_CLIENT_ACCESS. */
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH74, WarmbootCarveoutClientAccess0);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH75, WarmbootCarveoutClientAccess1);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH76, 0);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH77, 0);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH78, 0);
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/* Save MC_SECURITY_CARVEOUT4_FORCE_INTERNAL_ACCESS. */
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH99, WarmbootCarveoutForceInternalAccess0);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH100, WarmbootCarveoutForceInternalAccess1);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH101, 0);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH102, 0);
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reg::Write(PMC + APBDEV_PMC_SECURE_SCRATCH103, 0);
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/* Save MC_SECURITY_CARVEOUT4_CFG0. */
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reg::ReadWrite(PMC + APBDEV_PMC_SECURE_SCRATCH39, REG_BITS_VALUE(0, 27, WarmbootCarveoutConfig));
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}
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void EnableBpmpSmmu() {
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/* Define the ASID contents. */
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constexpr int BpmpAsid = 1;
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constexpr uintptr_t BpmpAsidPde = MemoryRegionPhysicalDeviceSecurityEngine.GetAddress();
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/* Configure the ASID. */
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reg::Write(MC + MC_SMMU_PTB_ASID, MC_REG_BITS_VALUE(SMMU_PTB_ASID_CURRENT_ASID, BpmpAsid));
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reg::Write(MC + MC_SMMU_PTB_DATA, MC_REG_BITS_VALUE(SMMU_PTB_DATA_ASID_PDE_BASE, BpmpAsidPde / 4_KB),
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MC_REG_BITS_ENUM (SMMU_PTB_DATA_ASID_NONSECURE, DISABLE),
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MC_REG_BITS_ENUM (SMMU_PTB_DATA_ASID_WRITABLE, DISABLE),
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MC_REG_BITS_ENUM (SMMU_PTB_DATA_ASID_READABLE, DISABLE));
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/* Configure the BPMP and PPCS1 to use the asid. */
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reg::Write(MC + MC_SMMU_AVPC_ASID, MC_REG_BITS_ENUM(SMMU_AVPC_ASID_AVPC_SMMU_ENABLE, ENABLE), MC_REG_BITS_VALUE(SMMU_AVPC_ASID_AVPC_ASID, BpmpAsid));
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reg::Write(MC + MC_SMMU_PPCS1_ASID, MC_REG_BITS_ENUM(SMMU_PPCS1_ASID_PPCS1_SMMU_ENABLE, ENABLE), MC_REG_BITS_VALUE(SMMU_PPCS1_ASID_PPCS1_ASID, BpmpAsid));
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/* Flush the entire page table cache, and read TLB_CONFIG to ensure the flush takes. */
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reg::Write(MC + MC_SMMU_PTC_FLUSH, 0);
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reg::Read (MC + MC_SMMU_TLB_CONFIG);
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/* Flush the entire translation lookaside buffer, and read TLB_CONFIG to ensure the flush takes. */
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reg::Write(MC + MC_SMMU_TLB_FLUSH, 0);
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reg::Read (MC + MC_SMMU_TLB_CONFIG);
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}
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void ActmonInterruptHandler() {
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SetError(pkg1::ErrorInfo_ActivityMonitorInterrupt);
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AMS_ABORT("actmon observed bpmp wakeup");
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}
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}
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void Setup1() {
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@ -783,7 +953,7 @@ namespace ams::secmon {
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SetupSmmu();
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/* Clear the cpu reset vector. */
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reg::Write(secmon::MemoryRegionVirtualDeviceExceptionVectors.GetAddress() + EVP_CPU_RESET_VECTOR, 0);
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reg::Write(EVP + EVP_CPU_RESET_VECTOR, 0);
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/* Configure the SB registers to our start address. */
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constexpr u32 ResetVectorLow = static_cast<u32>((PhysicalTzramProgramResetVector >> 0));
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@ -836,8 +1006,51 @@ namespace ams::secmon {
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}
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}
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void SetupSocSecurityWarmboot() {
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/* ... */
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}
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void SetupSocProtections() {
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/* TODO */
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/* Setup the GPU carveout. */
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SetupGpuCarveout();
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/* Disable the ARC. */
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DisableArc();
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/* Finalize and lock the carveout scratch registers. */
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FinalizeCarveoutSecureScratchRegisters();
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pmc::LockSecureRegister(pmc::SecureRegister_Carveout);
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/* Clear all the BPMP exception vectors to a fixed value. */
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constexpr u32 BpmpExceptionVector = 0x7D000000;
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reg::Write(EVP + EVP_COP_RESET_VECTOR, BpmpExceptionVector);
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reg::Write(EVP + EVP_COP_UNDEF_VECTOR, BpmpExceptionVector);
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reg::Write(EVP + EVP_COP_SWI_VECTOR, BpmpExceptionVector);
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reg::Write(EVP + EVP_COP_PREFETCH_ABORT_VECTOR, BpmpExceptionVector);
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reg::Write(EVP + EVP_COP_DATA_ABORT_VECTOR, BpmpExceptionVector);
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reg::Write(EVP + EVP_COP_RSVD_VECTOR, BpmpExceptionVector);
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reg::Write(EVP + EVP_COP_IRQ_VECTOR, BpmpExceptionVector);
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reg::Write(EVP + EVP_COP_FIQ_VECTOR, BpmpExceptionVector);
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/* Turn on the SMMU for the BPMP. */
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EnableBpmpSmmu();
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/* Wait until the flow controller reports that the BPMP is halted. */
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while (!reg::HasValue(FLOW_CTLR + FLOW_CTLR_HALT_COP_EVENTS, FLOW_REG_BITS_ENUM(HALT_COP_EVENTS_MODE, FLOW_MODE_STOP))) {
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util::WaitMicroSeconds(1);
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}
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/* If JTAG is disabled, disable JTAG. */
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if (!secmon::IsJtagEnabled()) {
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reg::Write(FLOW_CTLR + FLOW_CTLR_HALT_COP_EVENTS, FLOW_REG_BITS_ENUM(HALT_COP_EVENTS_MODE, FLOW_MODE_STOP),
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FLOW_REG_BITS_ENUM(HALT_COP_EVENTS_JTAG, DISABLED));
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/* If version is above 4.0.0, turn on the activity monitor to prevent booting up the bpmp. */
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if (GetTargetFirmware() >= TargetFirmware_4_0_0) {
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clkrst::EnableActmonClock();
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actmon::StartMonitoringBpmp(ActmonInterruptHandler);
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}
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}
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}
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void SetupPmcAndMcSecure() {
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