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exo2: implement through end of random cache init
This commit is contained in:
Michael Scire
SciresM
parent
f66b41c027
commit
cbcd1d87fb
11 changed files with 447 additions and 11 deletions
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@ -26,6 +26,7 @@
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#include <exosphere/pkg1.hpp>
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#include <exosphere/tsec.hpp>
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#include <exosphere/se.hpp>
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#include <exosphere/flow.hpp>
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#include <exosphere/fuse.hpp>
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#include <exosphere/i2c.hpp>
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#include <exosphere/uart.hpp>
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25
libraries/libexosphere/include/exosphere/flow.hpp
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25
libraries/libexosphere/include/exosphere/flow.hpp
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@ -0,0 +1,25 @@
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours.hpp>
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namespace ams::flow {
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void SetRegisterAddress(uintptr_t address);
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void ResetCpuRegisters(int core);
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}
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@ -141,17 +141,79 @@ namespace ams::hw::arch::arm64 {
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#define HW_CPU_GET_DBGWCR3_EL1(value) HW_CPU_GET_SYSREG(dbgwcr3_el1, value)
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#define HW_CPU_SET_DBGWCR3_EL1(value) HW_CPU_SET_SYSREG(dbgwcr3_el1, value)
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#define HW_CPU_GET_CNTFRQ_EL0(value) HW_CPU_GET_SYSREG(cntfrq_el0, value)
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#define HW_CPU_SET_CNTFRQ_EL0(value) HW_CPU_SET_SYSREG(cntfrq_el0, value)
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#define HW_CPU_GET_CNTHCTL_EL2(value) HW_CPU_GET_SYSREG(cnthctl_el2, value)
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#define HW_CPU_SET_CNTHCTL_EL2(value) HW_CPU_SET_SYSREG(cnthctl_el2, value)
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#define HW_CPU_GET_ACTLR_EL2(value) HW_CPU_GET_SYSREG(actlr_el2, value)
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#define HW_CPU_SET_ACTLR_EL2(value) HW_CPU_SET_SYSREG(actlr_el2, value)
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#define HW_CPU_GET_ACTLR_EL3(value) HW_CPU_GET_SYSREG(actlr_el3, value)
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#define HW_CPU_SET_ACTLR_EL3(value) HW_CPU_SET_SYSREG(actlr_el3, value)
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#define HW_CPU_GET_HCR_EL2(value) HW_CPU_GET_SYSREG(hcr_el2, value)
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#define HW_CPU_SET_HCR_EL2(value) HW_CPU_SET_SYSREG(hcr_el2, value)
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#define HW_CPU_GET_DACR32_EL2(value) HW_CPU_GET_SYSREG(dacr32_el2, value)
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#define HW_CPU_SET_DACR32_EL2(value) HW_CPU_SET_SYSREG(dacr32_el2, value)
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#define HW_CPU_GET_SCTLR_EL2(value) HW_CPU_GET_SYSREG(sctlr_el2, value)
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#define HW_CPU_SET_SCTLR_EL2(value) HW_CPU_SET_SYSREG(sctlr_el2, value)
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#define HW_CPU_GET_SCTLR_EL1(value) HW_CPU_GET_SYSREG(sctlr_el1, value)
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#define HW_CPU_SET_SCTLR_EL1(value) HW_CPU_SET_SYSREG(sctlr_el1, value)
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/* https://developer.arm.com/docs/ddi0488/h/system-control/aarch64-register-descriptions/system-control-register-el3 */
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struct SctlrEl3 {
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using M = util::BitPack32::Field< 0, 1>;
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using A = util::BitPack32::Field< 1, 1>;
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using C = util::BitPack32::Field< 2, 1>;
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using Sa = util::BitPack32::Field< 3, 1>;
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using I = util::BitPack32::Field<12, 1>;
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using Wxn = util::BitPack32::Field<19, 1>;
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using Ee = util::BitPack32::Field<25, 1>;
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using M = util::BitPack64::Field< 0, 1>;
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using A = util::BitPack64::Field< 1, 1>;
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using C = util::BitPack64::Field< 2, 1>;
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using Sa = util::BitPack64::Field< 3, 1>;
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using I = util::BitPack64::Field<12, 1>;
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using Wxn = util::BitPack64::Field<19, 1>;
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using Ee = util::BitPack64::Field<25, 1>;
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static constexpr u32 Res1 = 0x30C50830;
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static constexpr u64 Res1 = 0x30C50830;
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};
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/* https://static.docs.arm.com/ddi0487/fb/DDI0487F_b_armv8_arm.pdf */
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struct SctlrEl2 {
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using M = util::BitPack64::Field< 0, 1>;
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using A = util::BitPack64::Field< 1, 1>;
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using C = util::BitPack64::Field< 2, 1>;
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using Sa = util::BitPack64::Field< 3, 1>;
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using I = util::BitPack64::Field<12, 1>;
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using Wxn = util::BitPack64::Field<19, 1>;
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using Ee = util::BitPack64::Field<25, 1>;
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static constexpr u64 Res1 = 0x30C50830;
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};
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/* https://developer.arm.com/docs/ddi0488/h/system-control/aarch64-register-descriptions/system-control-register-el1 */
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struct SctlrEl1 {
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using M = util::BitPack64::Field< 0, 1>;
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using A = util::BitPack64::Field< 1, 1>;
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using C = util::BitPack64::Field< 2, 1>;
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using Sa = util::BitPack64::Field< 3, 1>;
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using Sa0 = util::BitPack64::Field< 4, 1>;
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using Cp15BEn = util::BitPack64::Field< 5, 1>;
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using Thee = util::BitPack64::Field< 6, 1>;
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using Itd = util::BitPack64::Field< 7, 1>;
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using Sed = util::BitPack64::Field< 8, 1>;
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using Uma = util::BitPack64::Field< 9, 1>;
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using I = util::BitPack64::Field<12, 1>;
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using Dze = util::BitPack64::Field<14, 1>;
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using Uct = util::BitPack64::Field<15, 1>;
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using Ntwi = util::BitPack64::Field<16, 1>;
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using Ntwe = util::BitPack64::Field<18, 1>;
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using Wxn = util::BitPack64::Field<19, 1>;
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using E0e = util::BitPack64::Field<24, 1>;
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using Ee = util::BitPack64::Field<25, 1>;
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using Uci = util::BitPack64::Field<26, 1>;
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static constexpr u64 Res1 = 0x30D00800;
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};
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/* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488c/BABGIHHJ.html */
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@ -242,4 +304,27 @@ namespace ams::hw::arch::arm64 {
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using Snid = util::BitPack32::Field<6, 2>;
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};
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}
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/* https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/cnthctl_el2 */
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struct CnthctlEl2 {
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using El1PctEn = util::BitPack32::Field<0, 1>;
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using El1PcEn = util::BitPack32::Field<1, 1>;
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using EvntEn = util::BitPack32::Field<2, 1>;
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using EvntDir = util::BitPack32::Field<3, 1>;
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using EvntI = util::BitPack32::Field<4, 4>;
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};
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/* https://developer.arm.com/docs/ddi0488/h/system-control/aarch64-register-descriptions/auxiliary-control-register-el3 */
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struct ActlrCortexA57 {
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using Cpuactlr = util::BitPack32::Field<0, 1>;
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using Cpuectlr = util::BitPack32::Field<1, 1>;
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using L2ctlr = util::BitPack32::Field<4, 1>;
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using L2ectlr = util::BitPack32::Field<5, 1>;
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using L2actlr = util::BitPack32::Field<6, 1>;
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};
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/* https://developer.arm.com/docs/ddi0488/h/system-control/aarch64-register-descriptions/hypervisor-configuration-register-el2 */
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struct HcrEl2 {
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using Rw = util::BitPack64::Field<31, 1>;
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};
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}
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@ -20,6 +20,21 @@
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#define FLOW_CTLR_FLOW_DBG_QUAL (0x050)
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#define FLOW_CTLR_BPMP_CLUSTER_CONTROL (0x098)
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#define FLOW_CTLR_CPU0_CSR (0x008)
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#define FLOW_CTLR_CPU1_CSR (0x018)
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#define FLOW_CTLR_CPU2_CSR (0x020)
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#define FLOW_CTLR_CPU3_CSR (0x028)
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#define FLOW_CTLR_HALT_CPU0_EVENTS (0x000)
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#define FLOW_CTLR_HALT_CPU1_EVENTS (0x014)
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#define FLOW_CTLR_HALT_CPU2_EVENTS (0x01C)
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#define FLOW_CTLR_HALT_CPU3_EVENTS (0x024)
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#define FLOW_CTLR_CC4_CORE0_CTRL (0x06C)
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#define FLOW_CTLR_CC4_CORE1_CTRL (0x070)
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#define FLOW_CTLR_CC4_CORE2_CTRL (0x074)
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#define FLOW_CTLR_CC4_CORE3_CTRL (0x078)
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#define FLOW_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (FLOW_CTLR, NAME)
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#define FLOW_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (FLOW_CTLR, NAME, VALUE)
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#define FLOW_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (FLOW_CTLR, NAME, ENUM)
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