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fusee_cpp: begin mariko mtc work

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Michael Scire 2021-09-01 19:06:46 -07:00 • committed by SciresM
parent 598edc0a46
commit c4fee796ea
5 changed files with 292 additions and 14 deletions
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11
libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp
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@ -67,6 +67,15 @@
#define CLK_RST_CONTROLLER_PLLC4_BASE (0x5A4)
#define CLK_RST_CONTROLLER_PLLC_MISC2 (0x5D0)
#define CLK_RST_CONTROLLER_PLLMB_BASE (0x5E8)
#define CLK_RST_CONTROLLER_PLLMB_MISC1 (0x5EC)
/* Mariko. */
#define CLK_RST_CONTROLLER_PLLM_SS_CFG (0x774)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1 (0x778)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2 (0x77C)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG (0x780)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1 (0x784)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2 (0x788)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA (0x0F8)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB (0x0FC)
@ -118,6 +127,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_OUT_PLLC_OUT1_DIV_BYP, 16, DISABLE, ENABLE);
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVM, 0, 8);
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVN, 8, 8);
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVP, 20, 5);
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVP_B01, 20, 1);
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_LOCK, 27, NOT_LOCK, LOCK);
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_ENABLE, 30, DISABLE, ENABLE);
@ -167,6 +177,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_ENABLE, 30, DISABLE, ENABLE);
DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVM, 0, 8);
DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVN, 8, 8);
DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVP, 20, 5);
DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVP_B01, 20, 1);
DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_LOCK, 27, NOT_LOCK, LOCK);
DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE);