mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-05-29 14:05:17 -04:00
fusee-cpp: Implement mbist workaround
This commit is contained in:
Michael Scire
SciresM
parent
3e81796db7
commit
c333a84b6b
19 changed files with 847 additions and 35 deletions
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@ -29,6 +29,7 @@
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#include <vapours/tegra/tegra_evp.hpp>
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#include <vapours/tegra/tegra_flow_ctlr.hpp>
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#include <vapours/tegra/tegra_i2c.hpp>
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#include <vapours/tegra/tegra_i2s.hpp>
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#include <vapours/tegra/tegra_ictlr.hpp>
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#include <vapours/tegra/tegra_mc.hpp>
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#include <vapours/tegra/tegra_mipi_cal.hpp>
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@ -62,6 +62,11 @@ DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
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DEFINE_CLK_RST_REG_BIT_ENUM(OSC_CTRL_XOE, 0, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(OSC_CTRL_XOFS, 4, 6);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_CSI_CLK_SRC, 23, BRICK, PLL_D);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_ENABLE, 30, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_BYPASS, 31, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_BASE_PLLX_ENABLE, 30, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVISOR, 0, 8);
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@ -111,37 +116,48 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_ENABLE, 30, DISABLE, ENABLE);
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 (0x124)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 (0x128)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 (0x138)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_VI (0x148)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 (0x150)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 (0x154)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 (0x164)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X (0x180)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 (0x198)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 (0x1B8)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 (0x1BC)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE (0x1D4)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC (0x1F4)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT (0x3B4)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 (0x3C4)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 (0x410)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP (0x620)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF (0x62C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC (0x630)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 (0x65C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL (0x66C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM (0x694)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC (0x6A4)
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/* RST_DEV_*_SET */
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#define CLK_RST_CONTROLLER_RST_DEV_L_SET (0x300)
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#define CLK_RST_CONTROLLER_RST_DEV_H_SET (0x308)
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#define CLK_RST_CONTROLLER_RST_DEV_U_SET (0x310)
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#define CLK_RST_CONTROLLER_RST_DEV_V_SET (0x430)
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#define CLK_RST_CONTROLLER_RST_DEV_W_SET (0x438)
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#define CLK_RST_CONTROLLER_RST_DEV_X_SET (0x290)
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#define CLK_RST_CONTROLLER_RST_DEV_Y_SET (0x2A8)
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/* RST_DEV_*_CLR */
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#define CLK_RST_CONTROLLER_RST_DEV_L_CLR (0x304)
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#define CLK_RST_CONTROLLER_RST_DEV_H_CLR (0x30C)
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#define CLK_RST_CONTROLLER_RST_DEV_U_CLR (0x314)
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#define CLK_RST_CONTROLLER_RST_DEV_V_CLR (0x434)
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#define CLK_RST_CONTROLLER_RST_DEV_W_CLR (0x43C)
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#define CLK_RST_CONTROLLER_RST_DEV_X_CLR (0x294)
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#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR (0x2AC)
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/* CLK_ENB_*_SET */
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#define CLK_RST_CONTROLLER_CLK_ENB_L_SET (0x320)
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@ -193,6 +209,13 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_ENABLE, 30, DISABLE, ENABLE);
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#define CLK_RST_CONTROLLER_CLK_ENB_ACTMON_INDEX (0x17)
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#define CLK_RST_CONTROLLER_CLK_ENB_HOST1X_INDEX (0x1C)
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#define CLK_RST_CONTROLLER_CLK_ENB_TSEC_INDEX (0x13)
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#define CLK_RST_CONTROLLER_CLK_ENB_SOR0_INDEX (0x16)
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#define CLK_RST_CONTROLLER_CLK_ENB_SOR1_INDEX (0x17)
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#define CLK_RST_CONTROLLER_CLK_ENB_SOR_SAFE_INDEX (0x1E)
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#define CLK_RST_CONTROLLER_CLK_ENB_KFUSE_INDEX (0x08)
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/* RST_CPUG_CMPLX_* */
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET (0x450)
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR (0x454)
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@ -235,6 +258,19 @@ DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTA_UARTA_CLK_SRC, 29, PLLP_OUT0,
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTB_UARTB_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_VI_VI_CLK_SRC, 29, RESERVED0, PLLC2_OUT0, PLLC_OUT, PLLC3_OUT0, PLLP_OUT0, CLK_M, PLLA1_OUT0, PLLC4_OUT0);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_HOST1X_HOST1X_CLK_SRC, 29, PLLC4_OUT1, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT2, PLLP_OUT0, CLK_M, PLLA_OUT0, PLLC4_OUT0);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_NVENC_NVENC_CLK_SRC, 29, RESERVED0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, PLLP_OUT0, RESERVED5, PLLA1_OUT0, CLK_M);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_TSEC_TSEC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, RESERVED4, PLLA1_OUT0, CLK_M, PLLC4_OUT0);
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DEFINE_CLK_RST_REG_BIT_ENUM(CLK_SOURCE_SOR1_SOR1_CLK_SEL0, 14, MUX, SOR1_BRICK_OUTPUT);
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DEFINE_CLK_RST_REG_BIT_ENUM(CLK_SOURCE_SOR1_SOR1_CLK_SEL1, 15, SAFE_CLOCK, SOR1_CLOCK_SWITCH);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SOR1_SOR1_CLK_SRC, 29, PLLP_OUT0, RESERVED1, PLLD_OUT0, RESERVED3, RESERVED4, PLLD2_OUT0, CLK_M, RESERVED7);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_MSELECT_MSELECT_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT2, PLLC4_OUT1, CLK_S, CLK_M, PLLC4_OUT0);
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DEFINE_CLK_RST_REG(CLK_SOURCE_MSELECT_MSELECT_CLK_DIVISOR, 0, 8);
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@ -302,6 +338,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENA
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HANDLER(U, CRAM2, 2, 24) \
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HANDLER(V, CPUG, 3, 0) \
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HANDLER(V, MSELECT, 3, 3) \
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HANDLER(V, APB2APE, 3, 11) \
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HANDLER(V, SPDIF_DOUBLER, 3, 22) \
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HANDLER(V, ACTMON, 3, 23) \
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HANDLER(V, TZRAM, 3, 30) \
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@ -322,10 +359,12 @@ DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENA
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HANDLER(X, MC_BBC, 5, 10) \
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HANDLER(X, EMC_DLL, 5, 14) \
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HANDLER(X, UART_FST_MIPI_CAL, 5, 17) \
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HANDLER(X, VIC, 5, 18) \
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HANDLER(X, GPU, 5, 24) \
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HANDLER(X, DBGAPB, 5, 25) \
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HANDLER(X, PLLG_REF, 5, 29) \
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HANDLER(Y, LEGACY_TM, 6, 1) \
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HANDLER(Y, APE, 6, 6) \
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HANDLER(Y, MC_CCPA, 6, 8) \
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HANDLER(Y, MC_CDPA, 6, 9) \
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HANDLER(Y, PLLP_OUT_CPU, 6, 31)
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52
libraries/libvapours/include/vapours/tegra/tegra_i2s.hpp
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52
libraries/libvapours/include/vapours/tegra/tegra_i2s.hpp
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@ -0,0 +1,52 @@
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours/common.hpp>
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#include <vapours/assert.hpp>
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#include <vapours/literals.hpp>
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#include <vapours/util.hpp>
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#include <vapours/results.hpp>
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#include <vapours/reg.hpp>
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#define I2S_REG(x) (0x702d1000 + x)
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#define I2S0_I2S_CG (0x088)
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#define I2S0_I2S_CTRL (0x0A0)
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#define I2S1_I2S_CG (0x188)
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#define I2S1_I2S_CTRL (0x1A0)
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#define I2S2_I2S_CG (0x288)
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#define I2S2_I2S_CTRL (0x2A0)
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#define I2S3_I2S_CG (0x388)
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#define I2S3_I2S_CTRL (0x3A0)
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#define I2S4_I2S_CG (0x488)
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#define I2S4_I2S_CTRL (0x4A0)
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#define I2S_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (I2S, NAME)
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#define I2S_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (I2S, NAME, VALUE)
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#define I2S_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (I2S, NAME, ENUM)
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#define I2S_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(I2S, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
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#define DEFINE_I2S_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (I2S, NAME, __OFFSET__, __WIDTH__)
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#define DEFINE_I2S_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (I2S, NAME, __OFFSET__, ZERO, ONE)
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#define DEFINE_I2S_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (I2S, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
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#define DEFINE_I2S_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(I2S, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
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#define DEFINE_I2S_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (I2S, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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DEFINE_I2S_REG_BIT_ENUM(I2S_CG_SLCG_ENABLE, 0, FALSE, TRUE);
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DEFINE_I2S_REG_BIT_ENUM(I2S_CTRL_MASTER, 10, DISABLE, ENABLE);
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@ -58,6 +58,7 @@
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#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170)
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#define APBDEV_PMC_OSC_EDPD_OVER (0x1A4)
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#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8)
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#define APBDEV_PMC_RST_STATUS (0x1B4)
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#define APBDEV_PMC_IO_DPD_REQ (0x1B8)
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#define APBDEV_PMC_IO_DPD_STATUS (0x1BC)
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#define APBDEV_PMC_IO_DPD2_REQ (0x1C0)
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@ -65,6 +66,7 @@
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#define APBDEV_PMC_SEL_DPD_TIM (0x1C8)
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#define APBDEV_PMC_SCRATCH45 (0x234)
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#define APBDEV_PMC_SCRATCH46 (0x238)
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#define APBDEV_PMC_SCRATCH49 (0x244)
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#define APBDEV_PMC_TSC_MULT (0x2B4)
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#define APBDEV_PMC_STICKY_BITS (0x2C0)
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#define APBDEV_PMC_WEAK_BIAS (0x2C8)
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