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https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-05-28 05:34:11 -04:00
fusee-cpp: Implement mbist workaround
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parent
3e81796db7
commit
c333a84b6b
19 changed files with 847 additions and 35 deletions
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@ -62,11 +62,21 @@ namespace ams::clkrst {
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.reset_offset = CLK_RST_CONTROLLER_RST_DEVICES_##_REG_, \
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.clk_enb_offset = CLK_RST_CONTROLLER_CLK_OUT_ENB_##_REG_, \
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.clk_src_offset = CLK_RST_CONTROLLER_CLK_SOURCE_##_NAME_, \
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.index = CLK_RST_CONTROLLER_CLK_ENB_##_NAME_##_INDEX, \
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.index = CLK_RST_CONTROLLER_CLK_ENB_##_NAME_##_INDEX, \
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.clk_src = CLK_RST_CONTROLLER_CLK_SOURCE_##_NAME_##_##_NAME_##_CLK_SRC_##_CLK_, \
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.clk_div = _DIV_, \
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}
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#define DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(_VARNAME_, _REG_, _NAME_) \
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constexpr inline const ClockParameters _VARNAME_ = { \
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.reset_offset = CLK_RST_CONTROLLER_RST_DEVICES_##_REG_, \
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.clk_enb_offset = CLK_RST_CONTROLLER_CLK_OUT_ENB_##_REG_, \
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.clk_src_offset = 0, \
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.index = CLK_RST_CONTROLLER_CLK_ENB_##_NAME_##_INDEX, \
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.clk_src = 0, \
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.clk_div = 0, \
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}
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DEFINE_CLOCK_PARAMETERS(UartAClock, L, UARTA, PLLP_OUT0, 0);
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DEFINE_CLOCK_PARAMETERS(UartBClock, L, UARTB, PLLP_OUT0, 0);
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DEFINE_CLOCK_PARAMETERS(UartCClock, H, UARTC, PLLP_OUT0, 0);
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@ -74,6 +84,14 @@ namespace ams::clkrst {
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DEFINE_CLOCK_PARAMETERS(I2c5Clock, H, I2C5, CLK_M, 0);
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DEFINE_CLOCK_PARAMETERS(ActmonClock, V, ACTMON, CLK_M, 0);
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DEFINE_CLOCK_PARAMETERS(Host1xClock, L, HOST1X, PLLP_OUT0, 3);
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DEFINE_CLOCK_PARAMETERS(TsecClock, U, TSEC, PLLP_OUT0, 2);
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DEFINE_CLOCK_PARAMETERS(Sor1Clock, X, SOR1, PLLP_OUT0, 2);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(SorSafeClock, Y, SOR_SAFE);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(Sor0Clock, X, SOR0);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(KfuseClock, H, KFUSE);
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}
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void SetRegisterAddress(uintptr_t address) {
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@ -108,8 +126,56 @@ namespace ams::clkrst {
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EnableClock(I2c5Clock);
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}
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void EnableHost1xClock() {
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EnableClock(Host1xClock);
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}
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void EnableTsecClock() {
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EnableClock(TsecClock);
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}
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void EnableSorSafeClock() {
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EnableClock(SorSafeClock);
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}
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void EnableSor0Clock() {
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EnableClock(Sor0Clock);
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}
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void EnableSor1Clock() {
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EnableClock(Sor1Clock);
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}
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void EnableKfuseClock() {
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EnableClock(KfuseClock);
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}
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void DisableI2c1Clock() {
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DisableClock(I2c1Clock);
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}
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void DisableHost1xClock() {
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DisableClock(Host1xClock);
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}
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void DisableTsecClock() {
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DisableClock(TsecClock);
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}
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void DisableSorSafeClock() {
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DisableClock(SorSafeClock);
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}
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void DisableSor0Clock() {
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DisableClock(Sor0Clock);
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}
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void DisableSor1Clock() {
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DisableClock(Sor1Clock);
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}
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void DisableKfuseClock() {
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DisableClock(KfuseClock);
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}
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}
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@ -432,6 +432,19 @@ namespace ams::fuse {
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return reg::HasValue(GetChipRegistersCommon().FUSE_SECURITY_MODE, FUSE_REG_BITS_ENUM(SECURITY_MODE_SECURITY_MODE, ENABLED));
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}
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bool GetSecureBootKey(void *dst) {
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/* Get the sbk from fuse data. */
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bool valid = false;
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for (size_t i = 0; i < 4; ++i) {
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const u32 key_word = GetChipRegistersCommon().FUSE_PRIVATE_KEY[i];
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static_cast<u32 *>(dst)[i] = key_word;
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valid |= key_word != 0xFFFFFFFF;
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}
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return valid;
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}
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void ConfigureFuseBypass() {
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/* Make the fuse registers visible. */
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clkrst::SetFuseVisibility(true);
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@ -19,8 +19,41 @@ namespace ams::tsec {
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namespace {
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enum TsecResult {
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TsecResult_Success = 0xB0B0B0B0,
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TsecResult_Failure = 0xD0D0D0D0,
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};
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bool RunFirmwareImpl(const void *fw, size_t fw_size) {
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/* Enable relevant clocks. */
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clkrst::EnableHost1xClock();
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clkrst::EnableTsecClock();
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clkrst::EnableSorSafeClock();
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clkrst::EnableSor0Clock();
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clkrst::EnableSor1Clock();
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clkrst::EnableKfuseClock();
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/* Disable clocks once we're done. */
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ON_SCOPE_EXIT {
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clkrst::DisableHost1xClock();
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clkrst::DisableTsecClock();
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clkrst::DisableSorSafeClock();
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clkrst::DisableSor0Clock();
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clkrst::DisableSor1Clock();
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clkrst::DisableKfuseClock();
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};
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/* TODO */
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AMS_UNUSED(fw, fw_size);
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return true;
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}
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}
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bool RunTsecFirmware(const void *fw, size_t fw_size) {
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/* TODO */
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AMS_UNUSED(fw, fw_size);
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return RunFirmwareImpl(fw, fw_size);
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}
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void Lock() {
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