mirrors/Atmosphere
1
0
Fork 0
mirror of https://github.com/Atmosphere-NX/Atmosphere.git synced 2025-06-06 09:31:16 -04:00
Code Issues Projects Releases Packages Wiki Activity

adding UartVendorStatus, UartLineStatus and UartLineControl

Browse source 
refactor defines
edited uart_wait_idle() second parameter type to UartVendorStatus
This commit is contained in:
Resaec 2018-04-27 23:57:20 +02:00
parent b34b9ba0e4
commit ae69126509
2 changed files with 56 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

55
exosphere/src/uart.h
View file

@ -13,6 +13,8 @@ static inline uintptr_t get_uart_base(void) {
#define UART_BASE (get_uart_base())
#define BAUD_115200 115200
/* Exosphère: add the clkreset values for UART C,D,E */
typedef enum {
UART_A = 0,
@ -22,12 +24,53 @@ typedef enum {
UART_E = 4,
} UartDevice;
#define BAUD_115200 115200
typedef enum {
UART_TX_IDLE = 1 << 0,
UART_RX_IDLE = 1 << 1,
#define UART_TX_IDLE 0x00000001
#define UART_RX_IDLE 0x00000002
#define UART_TX_FIFO_FULL 0x100
#define UART_RX_FIFO_EMPTY 0x200
/* This bit is set to 1 when a read is issued to an empty FIFO and gets cleared on register read (sticky bit until read)
0 = NO_UNDERRUN
1 = UNDERRUN */
UART_UNDERRUN = 1 << 2,
/* This bit is set to 1 when write data is issued to the TX FIFO when it is already full and gets cleared on register read (sticky bit until read)
0 = NO_OVERRUN
1 = OVERRUN */
UART_OVERRUN = 1 << 3,
RX_FIFO_COUNTER = 0b111111 << 16, /* reflects number of current entries in RX FIFO */
TX_FIFO_COUNTER = 0b111111 << 24 /* reflects number of current entries in TX FIFO */
} UartVendorStatus;
typedef enum {
UART_LSR_RDR = 1 << 0, /* Receiver Data Ready */
UART_LSR_OVRF = 1 << 1, /* Receiver Overrun Error */
UART_LSR_PERR = 1 << 2, /* Parity Error */
UART_LSR_FERR = 1 << 3, /* Framing Error */
UART_LSR_BRK = 1 << 4, /* BREAK condition detected on line */
UART_LSR_THRE = 1 << 5, /* Transmit Holding Register is Empty -- OK to write data */
UART_LSR_TMTY = 1 << 6, /* Transmit Shift Register empty status */
UART_LSR_FIFOE = 1 << 7, /* Receive FIFO Error */
UART_LSR_TX_FIFO_FULL = 1 << 8, /* Transmitter FIFO full status */
UART_LSR_RX_FIFO_EMPTY = 1 << 9, /* Receiver FIFO empty status */
} UartLineStatus;
typedef enum {
UART_LCR_WD_LENGTH_5 = 0, /* word length 5 */
UART_LCR_WD_LENGTH_6 = 1, /* word length 6 */
UART_LCR_WD_LENGTH_7 = 2, /* word length 7 */
UART_LCR_WD_LENGTH_8 = 3, /* word length 8 */
/* STOP:
0 = Transmit 1 stop bit
1 = Transmit 2 stop bits (receiver always checks for 1 stop bit) */
UART_LCR_STOP = 1 << 2,
UART_LCR_PAR = 1 << 3, /* Parity enabled */
UART_LCR_EVEN = 1 << 4, /* Even parity format. There will always be an even number of 1s in the binary representation (PAR = 1) */
UART_LCR_SET_P = 1 << 5, /* Set (force) parity to value in LCR[4] */
UART_LCR_SET_B = 1 << 6, /* Set BREAK condition -- Transmitter sends all zeroes to indicate BREAK */
UART_LCR_DLAB = 1 << 7, /* Divisor Latch Access Bit (set to allow programming of the DLH, DLM Divisors) */
} UartLineControl;
typedef struct {
/* 0x00 */ uint32_t UART_THR_DLAB;
@ -48,7 +91,7 @@ typedef struct {
void uart_select(UartDevice dev);
void uart_init(UartDevice dev, uint32_t baud);
void uart_wait_idle(UartDevice dev, uint32_t which);
void uart_wait_idle(UartDevice dev, UartVendorStatus status);
void uart_send(UartDevice dev, const void *buf, size_t len);
void uart_recv(UartDevice dev, void *buf, size_t len);