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Refactor 32-bit register definitions

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This commit is contained in:
TuxSH 2018-03-03 20:23:13 +01:00
parent c0f99fcd1c
commit a6c7a2c57e
26 changed files with 126 additions and 98 deletions
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12
exosphere/src/interrupt.h
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@ -24,7 +24,7 @@ static inline uintptr_t get_gicc_base(void) {
#define GICD_BASE (get_gicd_base())
#define GICC_BASE (get_gicc_base())
#define GICD_CTLR (*((volatile uint32_t *)(GICD_BASE + 0x000ull)))
#define GICD_CTLR MAKE_REG32(GICD_BASE + 0x000ull)
#define GICD_IGROUPR ((volatile uint32_t *)(GICD_BASE + 0x080ull))
#define GICD_ISENABLER ((volatile uint32_t *)(GICD_BASE + 0x100ull))
#define GICD_ISPENDR ((volatile uint32_t *)(GICD_BASE + 0x200ull))
@ -32,11 +32,11 @@ static inline uintptr_t get_gicc_base(void) {
#define GICD_ITARGETSR ((volatile uint8_t *)(GICD_BASE + 0x800ull))
#define GICD_ICFGR ((volatile uint32_t *)(GICD_BASE + 0xC00ull))
#define GICC_CTLR (*((volatile uint32_t *)(GICC_BASE + 0x0000ull)))
#define GICC_PMR (*((volatile uint32_t *)(GICC_BASE + 0x0004ull)))
#define GICC_BPR (*((volatile uint32_t *)(GICC_BASE + 0x0008ull)))
#define GICC_IAR (*((volatile uint32_t *)(GICC_BASE + 0x000CULL)))
#define GICC_EOIR (*((volatile uint32_t *)(GICC_BASE + 0x0010ull)))
#define GICC_CTLR MAKE_REG32(GICC_BASE + 0x0000ull)
#define GICC_PMR MAKE_REG32(GICC_BASE + 0x0004ull)
#define GICC_BPR MAKE_REG32(GICC_BASE + 0x0008ull)
#define GICC_IAR MAKE_REG32(GICC_BASE + 0x000CULL)
#define GICC_EOIR MAKE_REG32(GICC_BASE + 0x0010ull)
#define GIC_PRI_HIGHEST_SECURE 0x00
#define GIC_PRI_HIGHEST_NONSECURE 0x80