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exo2: implement warmboot through start of virtual exec
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parent
dc6abf9f68
commit
81846fa5c3
2 changed files with 180 additions and 2 deletions
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@ -26,8 +26,12 @@ namespace ams::secmon {
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namespace {
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constexpr inline uintptr_t MC = MemoryRegionPhysicalDeviceMemoryController.GetAddress();
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using namespace ams::mmu;
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constexpr inline PageTableMappingAttribute MappingAttributesEl3SecureRwCode = AddMappingAttributeIndex(PageTableMappingAttributes_El3SecureRwCode, MemoryAttributeIndexNormal);
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void SetupCpuCommonControllers() {
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/* Set cpuactlr_el1. */
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{
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@ -146,6 +150,69 @@ namespace ams::secmon {
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hw::InstructionSynchronizationBarrier();
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}
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bool IsExitLp0() {
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return reg::Read(MC + MC_SECURITY_CFG3) == 0;
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}
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constexpr void AddPhysicalTzramIdentityMappingImpl(u64 *l1, u64 *l2, u64 *l3) {
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/* Define extents. */
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const uintptr_t start_address = MemoryRegionPhysicalTzram.GetAddress();
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const size_t size = MemoryRegionPhysicalTzram.GetSize();
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const uintptr_t end_address = start_address + size;
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/* Flush cache for the L3 page table entries. */
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{
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const uintptr_t start = GetL3EntryIndex(start_address);
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const uintptr_t end = GetL3EntryIndex(end_address);
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for (uintptr_t i = start; i < end; i += hw::DataCacheLineSize / sizeof(*l3)) {
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if (!std::is_constant_evaluated()) { hw::FlushDataCacheLine(l3 + i); }
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}
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}
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/* Flush cache for the L2 page table entry. */
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if (!std::is_constant_evaluated()) { hw::FlushDataCacheLine(l2 + GetL2EntryIndex(start_address)); }
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/* Flush cache for the L1 page table entry. */
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if (!std::is_constant_evaluated()) { hw::FlushDataCacheLine(l1 + GetL1EntryIndex(start_address)); }
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/* Add the L3 mappings. */
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SetL3BlockEntry(l3, start_address, start_address, size, MappingAttributesEl3SecureRwCode);
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/* Add the L2 entry for the physical tzram region. */
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SetL2TableEntry(l2, MemoryRegionPhysicalTzramL2.GetAddress(), MemoryRegionPhysicalTzramL2L3PageTable.GetAddress(), PageTableTableAttributes_El3SecureCode);
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/* Add the L1 entry for the physical region. */
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SetL1TableEntry(l1, MemoryRegionPhysical.GetAddress(), MemoryRegionPhysicalTzramL2L3PageTable.GetAddress(), PageTableTableAttributes_El3SecureCode);
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static_assert(GetL1EntryIndex(MemoryRegionPhysical.GetAddress()) == 1);
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/* Invalidate the data cache for the L3 page table entries. */
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{
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const uintptr_t start = GetL3EntryIndex(start_address);
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const uintptr_t end = GetL3EntryIndex(end_address);
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for (uintptr_t i = start; i < end; i += hw::DataCacheLineSize / sizeof(*l3)) {
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if (!std::is_constant_evaluated()) { hw::InvalidateDataCacheLine(l3 + i); }
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}
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}
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/* Flush cache for the L2 page table entry. */
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if (!std::is_constant_evaluated()) { hw::InvalidateDataCacheLine(l2 + GetL2EntryIndex(start_address)); }
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/* Flush cache for the L1 page table entry. */
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if (!std::is_constant_evaluated()) { hw::InvalidateDataCacheLine(l1 + GetL1EntryIndex(start_address)); }
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}
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void AddPhysicalTzramIdentityMapping() {
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/* Get page table extents. */
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u64 * const l1 = MemoryRegionPhysicalTzramL1PageTable.GetPointer<u64>();
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u64 * const l2_l3 = MemoryRegionPhysicalTzramL2L3PageTable.GetPointer<u64>();
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/* Add the mapping. */
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AddPhysicalTzramIdentityMappingImpl(l1, l2_l3, l2_l3);
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/* Ensure that mappings are consistent. */
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setup::EnsureMappingConsistency();
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}
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}
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void SetupCpuMemoryControllersEnableMmu() {
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@ -204,7 +271,16 @@ namespace ams::secmon {
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}
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void SetupSocDmaControllersCpuMemoryControllersEnableMmuWarmboot() {
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/* TODO */
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/* If this is being called from lp0 exit, we want to setup the soc dma controllers. */
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if (IsExitLp0()) {
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SetupSocDmaControllers();
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}
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/* Add a physical TZRAM identity map. */
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AddPhysicalTzramIdentityMapping();
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/* Initialize cpu memory controllers and the MMU. */
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SetupCpuMemoryControllersEnableMmu();
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}
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}
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