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kern: implement debug register/vectors init
This commit is contained in:
Michael Scire
parent
7c703903ea
commit
7820e5b759
3 changed files with 297 additions and 2 deletions
141
mesosphere/kernel/source/arch/arm64/exception_vectors.s
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141
mesosphere/kernel/source/arch/arm64/exception_vectors.s
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* Some macros taken from https://github.com/ARM-software/arm-trusted-firmware/blob/master/include/common/aarch64/asm_macros.S */
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/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Declare the exception vector table, enforcing it is aligned on a
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* 2KB boundary, as required by the ARMv8 architecture.
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* Use zero bytes as the fill value to be stored in the padding bytes
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* so that it inserts illegal AArch64 instructions. This increases
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* security, robustness and potentially facilitates debugging.
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*/
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.macro vector_base label, section_name=.vectors
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.section \section_name, "ax"
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.align 11, 0
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\label:
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.endm
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/*
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* Create an entry in the exception vector table, enforcing it is
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* aligned on a 128-byte boundary, as required by the ARMv8 architecture.
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* Use zero bytes as the fill value to be stored in the padding bytes
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* so that it inserts illegal AArch64 instructions. This increases
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* security, robustness and potentially facilitates debugging.
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*/
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.macro vector_entry label, section_name=.vectors
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.cfi_sections .debug_frame
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.section \section_name, "ax"
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.align 7, 0
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.type \label, %function
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.func \label
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.cfi_startproc
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\label:
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.endm
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/*
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* This macro verifies that the given vector doesnt exceed the
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* architectural limit of 32 instructions. This is meant to be placed
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* immediately after the last instruction in the vector. It takes the
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* vector entry as the parameter
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*/
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.macro check_vector_size since
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.endfunc
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.cfi_endproc
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.if (. - \since) > (32 * 4)
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.error "Vector exceeds 32 instructions"
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.endif
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.endm
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/* Actual Vectors for Kernel. */
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.global _ZN3ams4kern16ExceptionVectorsEv
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vector_base _ZN3ams4kern16ExceptionVectorsEv
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/* Current EL, SP0 */
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.global unknown_exception
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unknown_exception:
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vector_entry synch_sp0
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/* Just infinite loop. */
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b unknown_exception
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check_vector_size synch_sp0
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vector_entry irq_sp0
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b unknown_exception
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check_vector_size irq_sp0
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vector_entry fiq_sp0
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b unknown_exception
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check_vector_size fiq_sp0
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vector_entry serror_sp0
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b unknown_exception
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check_vector_size serror_sp0
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/* Current EL, SPx */
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vector_entry synch_spx
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b unknown_exception
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check_vector_size synch_spx
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vector_entry irq_spx
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b unknown_exception
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check_vector_size irq_spx
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vector_entry fiq_spx
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b unknown_exception
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check_vector_size fiq_spx
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vector_entry serror_spx
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b unknown_exception
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check_vector_size serror_spx
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/* Lower EL, A64 */
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vector_entry synch_a64
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b unknown_exception
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check_vector_size synch_a64
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vector_entry irq_a64
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b unknown_exception
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check_vector_size irq_a64
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vector_entry fiq_a64
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b unknown_exception
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check_vector_size fiq_a64
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vector_entry serror_a64
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b unknown_exception
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check_vector_size serror_a64
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/* Lower EL, A32 */
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vector_entry synch_a32
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b unknown_exception
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check_vector_size synch_a32
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vector_entry irq_a32
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b unknown_exception
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check_vector_size irq_a32
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vector_entry fiq_a32
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b unknown_exception
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check_vector_size fiq_a32
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vector_entry serror_a32
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b unknown_exception
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check_vector_size serror_a32
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@ -18,6 +18,12 @@
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extern "C" void _start();
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extern "C" void __end__();
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namespace ams::kern {
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void ExceptionVectors();
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}
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namespace ams::kern::init {
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/* Prototypes for functions declared in ASM that we need to reference. */
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@ -310,11 +316,71 @@ namespace ams::kern::init {
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}
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void InitializeDebugRegisters() {
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/* TODO */
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/* Determine how many watchpoints and breakpoints we have */
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cpu::DebugFeatureRegisterAccessor aa64dfr0;
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const auto num_watchpoints = aa64dfr0.GetNumWatchpoints();
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const auto num_breakpoints = aa64dfr0.GetNumBreakpoints();
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cpu::EnsureInstructionConsistency();
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/* Clear the debug monitor register and the os lock access register. */
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cpu::MonitorDebugSystemControlRegisterAccessor(0).Store();
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cpu::EnsureInstructionConsistency();
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cpu::OsLockAccessRegisterAccessor(0).Store();
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cpu::EnsureInstructionConsistency();
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/* Clear all debug watchpoints/breakpoints. */
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#define FOR_I_IN_15_TO_1(HANDLER, ...) \
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HANDLER(15, ## __VA_ARGS__) HANDLER(14, ## __VA_ARGS__) HANDLER(13, ## __VA_ARGS__) HANDLER(12, ## __VA_ARGS__) \
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HANDLER(11, ## __VA_ARGS__) HANDLER(10, ## __VA_ARGS__) HANDLER(9, ## __VA_ARGS__) HANDLER(8, ## __VA_ARGS__) \
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HANDLER(7, ## __VA_ARGS__) HANDLER(6, ## __VA_ARGS__) HANDLER(5, ## __VA_ARGS__) HANDLER(4, ## __VA_ARGS__) \
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HANDLER(3, ## __VA_ARGS__) HANDLER(2, ## __VA_ARGS__) HANDLER(1, ## __VA_ARGS__)
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#define MESOSPHERE_INITIALIZE_WATCHPOINT_CASE(ID, ...) \
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case ID: \
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cpu::SetDbgWcr##ID##El1(__VA_ARGS__); \
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cpu::SetDbgWvr##ID##El1(__VA_ARGS__); \
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#define MESOSPHERE_INITIALIZE_BREAKPOINT_CASE(ID, ...) \
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case ID: \
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cpu::SetDbgBcr##ID##El1(__VA_ARGS__); \
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cpu::SetDbgBvr##ID##El1(__VA_ARGS__); \
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[[fallthrough]];
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switch (num_watchpoints) {
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FOR_I_IN_15_TO_1(MESOSPHERE_INITIALIZE_WATCHPOINT_CASE, 0)
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default:
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break;
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}
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cpu::SetDbgWcr0El1(0);
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cpu::SetDbgWvr0El1(0);
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switch (num_breakpoints) {
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FOR_I_IN_15_TO_1(MESOSPHERE_INITIALIZE_BREAKPOINT_CASE, 0)
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default:
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break;
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}
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cpu::SetDbgBcr0El1(0);
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cpu::SetDbgBvr0El1(0);
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#undef MESOSPHERE_INITIALIZE_WATCHPOINT_CASE
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#undef MESOSPHERE_INITIALIZE_BREAKPOINT_CASE
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#undef FOR_I_IN_15_TO_1
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cpu::EnsureInstructionConsistency();
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/* Initialize the context id register to all 1s. */
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cpu::ContextIdRegisterAccessor(0).SetProcId(std::numeric_limits<u32>::max()).Store();
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cpu::EnsureInstructionConsistency();
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/* Configure the debug monitor register. */
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cpu::MonitorDebugSystemControlRegisterAccessor(0).SetMde(true).SetTdcc(true).Store();
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cpu::EnsureInstructionConsistency();
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}
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void InitializeExceptionVectors() {
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/* TODO */
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cpu::SetVbarEl1(reinterpret_cast<uintptr_t>(::ams::kern::ExceptionVectors));
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cpu::EnsureInstructionConsistency();
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}
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}
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