thermosphere: use barriers and caches *properly*. Cache code refactoring

- set/way cache ops create losses of coherency, do not broadcast and are only meant to be used on boot, period.

Cache ops by VA are **the only way** to do data cache maintenance.

Fix a bug where the L2 cache was evicted by each core. It shouldn't have.

- Cleaning dcache to PoU and invalidating icache to PoU, by VA is sufficient for self-modifying code

- Since we operate within a single cluster and don't do DMA, we almost always operate within the inner shareability domain

(commit untested on real hw)

thermosphere/src/utils.h

@@ -62,6 +62,24 @@ typedef enum ReadWriteDirection {
     DIRECTION_READWRITE = DIRECTION_READ | DIRECTION_WRITE,
 } ReadWriteDirection;
 
+/*
+    Domains:
+        - Inner shareable: typically cores within a cluster (maybe more) with L1+L2 caches
+        - Outer shareable: all the cores in all clusters that can be coherent
+        - System: everything else
+    Since we only support 1 single cluster, we basically only need to consider the inner
+    shareable domain, except before doing DMA...
+*/
+static inline void __dmb(void)
+{
+    __asm__ __volatile__ ("dmb ish" ::: "memory");
+}
+
+static inline void __dsb(void)
+{
+    __asm__ __volatile__ ("dsb ish" ::: "memory");
+}
+
 static inline void __dmb_sy(void)
 {
     __asm__ __volatile__ ("dmb sy" ::: "memory");
@@ -77,6 +95,11 @@ static inline void __isb(void)
     __asm__ __volatile__ ("isb" ::: "memory");
 }
 
+static inline void __tlb_invalidate_el2(void)
+{
+    __asm__ __volatile__ ("tlbi alle2" ::: "memory");
+}
+
 static inline void __tlb_invalidate_el1_stage12(void)
 {
     __asm__ __volatile__ ("tlbi alle1" ::: "memory");