mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-06-01 07:18:22 -04:00
kern: refactor init (kill identity map, merge cpu on logic)
This commit is contained in:
Michael Scire
parent
42e6c1fd59
commit
709e1969bb
20 changed files with 431 additions and 387 deletions
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@ -353,12 +353,12 @@ namespace ams::kern::arch::arm64 {
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l1_entry->IsPrivilegedExecuteNever(),
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l1_entry->IsContiguous(),
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!l1_entry->IsGlobal(),
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static_cast<int>(l1_entry->GetAccessFlag()),
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static_cast<unsigned int>(l1_entry->GetShareable()),
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static_cast<int>(l1_entry->GetAccessFlagInteger()),
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static_cast<unsigned int>(l1_entry->GetShareableInteger()),
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l1_entry->IsReadOnly(),
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l1_entry->IsUserAccessible(),
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l1_entry->IsNonSecure(),
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static_cast<int>(l1_entry->GetPageAttribute()),
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static_cast<int>(l1_entry->GetPageAttributeInteger()),
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l1_entry->IsHeadMergeDisabled(),
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l1_entry->IsHeadAndBodyMergeDisabled(),
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l1_entry->IsTailMergeDisabled());
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@ -398,12 +398,12 @@ namespace ams::kern::arch::arm64 {
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l2_entry->IsPrivilegedExecuteNever(),
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l2_entry->IsContiguous(),
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!l2_entry->IsGlobal(),
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static_cast<int>(l2_entry->GetAccessFlag()),
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static_cast<unsigned int>(l2_entry->GetShareable()),
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static_cast<int>(l2_entry->GetAccessFlagInteger()),
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static_cast<unsigned int>(l2_entry->GetShareableInteger()),
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l2_entry->IsReadOnly(),
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l2_entry->IsUserAccessible(),
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l2_entry->IsNonSecure(),
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static_cast<int>(l2_entry->GetPageAttribute()),
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static_cast<int>(l2_entry->GetPageAttributeInteger()),
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l2_entry->IsHeadMergeDisabled(),
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l2_entry->IsHeadAndBodyMergeDisabled(),
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l2_entry->IsTailMergeDisabled());
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@ -443,12 +443,12 @@ namespace ams::kern::arch::arm64 {
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l3_entry->IsPrivilegedExecuteNever(),
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l3_entry->IsContiguous(),
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!l3_entry->IsGlobal(),
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static_cast<int>(l3_entry->GetAccessFlag()),
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static_cast<unsigned int>(l3_entry->GetShareable()),
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static_cast<int>(l3_entry->GetAccessFlagInteger()),
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static_cast<unsigned int>(l3_entry->GetShareableInteger()),
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l3_entry->IsReadOnly(),
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l3_entry->IsUserAccessible(),
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l3_entry->IsNonSecure(),
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static_cast<int>(l3_entry->GetPageAttribute()),
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static_cast<int>(l3_entry->GetPageAttributeInteger()),
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l3_entry->IsHeadMergeDisabled(),
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l3_entry->IsHeadAndBodyMergeDisabled(),
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l3_entry->IsTailMergeDisabled());
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@ -18,6 +18,12 @@
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#include "kern_secure_monitor.hpp"
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#include "kern_lps_driver.hpp"
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namespace ams::kern::init {
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void StartOtherCore(const ams::kern::init::KInitArguments *init_args);
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}
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namespace ams::kern::board::nintendo::nx {
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namespace {
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@ -67,15 +73,10 @@ namespace ams::kern::board::nintendo::nx {
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constinit KLightLock g_request_lock;
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constinit KLightLock g_cv_lock;
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constinit KLightConditionVariable g_cv{util::ConstantInitialize};
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constinit KPhysicalAddress g_sleep_buffer_phys_addrs[cpu::NumCores];
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alignas(1_KB) constinit u64 g_sleep_buffers[cpu::NumCores][1_KB / sizeof(u64)];
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constinit ams::kern::init::KInitArguments g_sleep_init_arguments[cpu::NumCores];
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constinit SavedSystemRegisters g_sleep_system_registers[cpu::NumCores] = {};
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void PowerOnCpu(int core_id, KPhysicalAddress entry_phys_addr, u64 context_id) {
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/* Request the secure monitor power on the core. */
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::ams::kern::arch::arm64::smc::CpuOn<smc::SmcId_Supervisor, true>(cpu::MultiprocessorAffinityRegisterAccessor().GetCpuOnArgument() | core_id, GetInteger(entry_phys_addr), context_id);
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}
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void WaitOtherCpuPowerOff() {
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constexpr u64 PmcPhysicalAddress = 0x7000E400;
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constexpr u32 PWRGATE_STATUS_CE123_MASK = ((1u << 3) - 1) << 9;
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@ -473,18 +474,20 @@ namespace ams::kern::board::nintendo::nx {
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}
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}
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void KSleepManager::ProcessRequests(uintptr_t buffer) {
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void KSleepManager::ProcessRequests(uintptr_t sleep_buffer) {
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const auto target_fw = GetTargetFirmware();
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const s32 core_id = GetCurrentCoreId();
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KPhysicalAddress resume_entry_phys_addr = Null<KPhysicalAddress>;
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ams::kern::init::KInitArguments * const init_args = g_sleep_init_arguments + core_id;
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KPhysicalAddress start_core_phys_addr = Null<KPhysicalAddress>;
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KPhysicalAddress init_args_phys_addr = Null<KPhysicalAddress>;
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/* Get the physical addresses we'll need. */
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{
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MESOSPHERE_ABORT_UNLESS(Kernel::GetKernelPageTable().GetPhysicalAddress(std::addressof(g_sleep_buffer_phys_addrs[core_id]), KProcessAddress(buffer)));
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MESOSPHERE_ABORT_UNLESS(Kernel::GetKernelPageTable().GetPhysicalAddress(std::addressof(resume_entry_phys_addr), KProcessAddress(&::ams::kern::board::nintendo::nx::KSleepManager::ResumeEntry)));
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MESOSPHERE_ABORT_UNLESS(Kernel::GetKernelPageTable().GetPhysicalAddress(std::addressof(start_core_phys_addr), KProcessAddress(&::ams::kern::init::StartOtherCore)));
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MESOSPHERE_ABORT_UNLESS(Kernel::GetKernelPageTable().GetPhysicalAddress(std::addressof(init_args_phys_addr), KProcessAddress(init_args)));
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}
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const KPhysicalAddress sleep_buffer_phys_addr = g_sleep_buffer_phys_addrs[core_id];
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const u64 target_core_mask = (1ul << core_id);
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const bool use_legacy_lps_driver = target_fw < TargetFirmware_2_0_0;
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@ -547,15 +550,29 @@ namespace ams::kern::board::nintendo::nx {
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/* Save the interrupt manager's state. */
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Kernel::GetInterruptManager().Save(core_id);
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/* Setup the initial arguments. */
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{
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init_args->ttbr0 = cpu::GetTtbr0El1();
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init_args->ttbr1 = cpu::GetTtbr1El1();
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init_args->tcr = cpu::GetTcrEl1();
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init_args->mair = cpu::GetMairEl1();
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init_args->cpuactlr = cpu::GetCpuActlrEl1();
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init_args->cpuectlr = cpu::GetCpuEctlrEl1();
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init_args->sctlr = cpu::GetSctlrEl1();
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init_args->sp = 0;
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init_args->entrypoint = reinterpret_cast<uintptr_t>(::ams::kern::board::nintendo::nx::KSleepManager::ResumeEntry);
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init_args->argument = sleep_buffer;
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}
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/* Ensure that all cores get to this point before continuing. */
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cpu::SynchronizeAllCores();
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/* Log that the core is going to sleep. */
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MESOSPHERE_LOG("Core[%d]: Going to sleep, buffer = %010lx\n", core_id, GetInteger(sleep_buffer_phys_addr));
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MESOSPHERE_LOG("Core[%d]: Going to sleep, buffer = %010lx\n", core_id, sleep_buffer);
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/* If we're on a core other than zero, we can just invoke the sleep handler. */
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if (core_id != 0) {
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CpuSleepHandler(GetInteger(sleep_buffer_phys_addr), GetInteger(resume_entry_phys_addr));
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CpuSleepHandler(sleep_buffer, GetInteger(start_core_phys_addr), GetInteger(init_args_phys_addr));
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} else {
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/* Wait for all other cores to be powered off. */
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WaitOtherCpuPowerOff();
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@ -574,9 +591,9 @@ namespace ams::kern::board::nintendo::nx {
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/* Invoke the sleep handler. */
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if (!use_legacy_lps_driver) {
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/* When not using the legacy driver, invoke directly. */
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CpuSleepHandler(GetInteger(sleep_buffer_phys_addr), GetInteger(resume_entry_phys_addr));
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CpuSleepHandler(sleep_buffer, GetInteger(start_core_phys_addr), GetInteger(init_args_phys_addr));
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} else {
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lps::InvokeCpuSleepHandler(GetInteger(sleep_buffer_phys_addr), GetInteger(resume_entry_phys_addr));
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lps::InvokeCpuSleepHandler(sleep_buffer, GetInteger(start_core_phys_addr), GetInteger(init_args_phys_addr));
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}
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/* Restore the debug log state. */
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@ -586,8 +603,10 @@ namespace ams::kern::board::nintendo::nx {
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MESOSPHERE_LOG("Exiting SC7\n");
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/* Wake up the other cores. */
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cpu::MultiprocessorAffinityRegisterAccessor mpidr;
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const auto arg = mpidr.GetCpuOnArgument();
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for (s32 i = 1; i < static_cast<s32>(cpu::NumCores); ++i) {
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PowerOnCpu(i, resume_entry_phys_addr, GetInteger(g_sleep_buffer_phys_addrs[i]));
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KSystemControl::Init::TurnOnCpu(arg | i, g_sleep_init_arguments + i);
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}
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}
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@ -22,14 +22,12 @@ namespace ams::kern::board::nintendo::nx {
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private:
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static void ResumeEntry(uintptr_t arg);
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static void InvalidateDataCacheForResumeEntry(uintptr_t level);
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static void ProcessRequests(uintptr_t buffer);
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public:
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static void Initialize();
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static void SleepSystem();
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public:
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static void CpuSleepHandler(uintptr_t arg, uintptr_t entry);
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static void CpuSleepHandler(uintptr_t arg, uintptr_t entry, uintptr_t entry_args);
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};
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@ -22,14 +22,14 @@
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mov reg, #(((val) >> 0x00) & 0xFFFF); \
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movk reg, #(((val) >> 0x10) & 0xFFFF), lsl#16
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/* ams::kern::board::nintendo::nx::KSleepManager::CpuSleepHandler(uintptr_t arg, uintptr_t entry) */
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.section .sleep._ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmm, "ax", %progbits
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.global _ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmm
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.type _ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmm, %function
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_ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmm:
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/* ams::kern::board::nintendo::nx::KSleepManager::CpuSleepHandler(uintptr_t arg, uintptr_t entry, uintptr_t entry_arg) */
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.section .sleep._ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmmm, "ax", %progbits
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.global _ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmmm
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.type _ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmmm, %function
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_ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmmm:
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/* Save arguments. */
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mov x16, x0
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mov x17, x1
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mov x16, x1
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mov x17, x2
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/* Enable access to FPU registers. */
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mrs x1, cpacr_el1
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@ -74,28 +74,8 @@ _ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmm:
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stp q28, q29, [x0], #0x20
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stp q30, q31, [x0], #0x20
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/* Save cpuactlr/cpuectlr. */
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mrs x1, cpuectlr_el1
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mrs x2, cpuactlr_el1
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stp x1, x2, [x0], #0x10
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/* Save ttbr0/ttbr1. */
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mrs x1, ttbr0_el1
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mrs x2, ttbr1_el1
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stp x1, x2, [x0], #0x10
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/* Save tcr/mair. */
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mrs x1, tcr_el1
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mrs x2, mair_el1
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stp x1, x2, [x0], #0x10
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/* Save sctlr/tpidr. */
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mrs x1, sctlr_el1
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mrs x2, tpidr_el1
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stp x1, x2, [x0], #0x10
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/* Save the virtual resumption entrypoint and cntv_cval_el0. */
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adr x1, 77f
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/* Save tpidr/cntv_cval_el0. */
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mrs x1, tpidr_el1
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mrs x2, cntv_cval_el0
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stp x1, x2, [x0], #0x10
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@ -114,8 +94,8 @@ _ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmm:
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1: /* Suspend. */
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LOAD_IMMEDIATE_32(x0, 0xC4000001)
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LOAD_IMMEDIATE_32(x1, 0x0201001B)
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mov x2, x17
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mov x3, x16
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mov x2, x16
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mov x3, x17
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smc #1
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0: b 0b
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@ -124,65 +104,6 @@ _ZN3ams4kern5board8nintendo2nx13KSleepManager15CpuSleepHandlerEmm:
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.global _ZN3ams4kern5board8nintendo2nx13KSleepManager11ResumeEntryEm
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.type _ZN3ams4kern5board8nintendo2nx13KSleepManager11ResumeEntryEm, %function
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_ZN3ams4kern5board8nintendo2nx13KSleepManager11ResumeEntryEm:
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/* Mask interrupts. */
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msr daifset, #0xF
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/* Save the argument. */
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mov x21, x0
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/* Check that we're at the correct exception level. */
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mrs x0, currentel
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/* Check if we're EL1. */
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cmp x0, #0x4
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b.eq 3f
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/* Check if we're EL2. */
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cmp x0, #0x8
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b.eq 2f
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1: /* We're running at EL3. */
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b 1b
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2: /* We're running at EL2. */
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b 2b
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3: /* We're running at EL1. */
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/* Invalidate the L1 cache. */
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mov x0, #0
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bl _ZN3ams4kern5board8nintendo2nx13KSleepManager33InvalidateDataCacheForResumeEntryEm
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/* Get the current core id. */
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mrs x0, mpidr_el1
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and x0, x0, #0xFF
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/* If we're on core0, we want to invalidate the L2 cache. */
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cbnz x0, 4f
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mov x0, #1
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bl _ZN3ams4kern5board8nintendo2nx13KSleepManager33InvalidateDataCacheForResumeEntryEm
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4: /* Invalidate the L1 cache. */
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mov x0, #0
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bl _ZN3ams4kern5board8nintendo2nx13KSleepManager33InvalidateDataCacheForResumeEntryEm
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/* Invalidate the instruction cache. */
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ic ialluis
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dsb sy
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isb
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/* Invalidate the entire tlb. */
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tlbi vmalle1is
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dsb sy
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isb
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/* Switch to sp 1. */
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msr spsel, #1
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/* Prepare to restore the saved context. */
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mov x0, x21
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/* Enable access to FPU registers. */
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mrs x1, cpacr_el1
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orr x1, x1, #0x100000
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@ -226,121 +147,12 @@ _ZN3ams4kern5board8nintendo2nx13KSleepManager11ResumeEntryEm:
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ldp q28, q29, [x0], #0x20
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ldp q30, q31, [x0], #0x20
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/* Restore cpuactlr/cpuectlr. */
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/* Restore tpidr/cntv_cval_el0. */
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ldp x1, x2, [x0], #0x10
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mrs x3, cpuectlr_el1
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cmp x1, x3
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5: b.ne 5b
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mrs x3, cpuactlr_el1
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cmp x2, x3
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6: b.ne 6b
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/* Restore ttbr0/ttbr1. */
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ldp x1, x2, [x0], #0x10
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msr ttbr0_el1, x1
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msr ttbr1_el1, x2
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/* Restore tcr/mair. */
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ldp x1, x2, [x0], #0x10
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msr tcr_el1, x1
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msr mair_el1, x2
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/* Get sctlr, tpidr, the entrypoint, and cntv_cval_el0. */
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ldp x1, x2, [x0], #0x10
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ldp x3, x4, [x0], #0x10
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/* Set the global context back into x18/tpidr. */
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msr tpidr_el1, x2
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msr cntv_cval_el0, x4
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dsb sy
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isb
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/* Restore sctlr with the wxn bit cleared. */
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bic x2, x1, #0x80000
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msr sctlr_el1, x2
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dsb sy
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isb
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/* Jump to the entrypoint. */
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br x3
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77: /* Virtual resumption entrypoint. */
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/* Restore sctlr. */
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msr sctlr_el1, x1
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msr tpidr_el1, x1
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msr cntv_cval_el0, x2
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dsb sy
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isb
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ret
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/* ams::kern::board::nintendo::nx::KSleepManager::InvalidateDataCacheForResumeEntry(uintptr_t level) */
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.section .sleep._ZN3ams4kern5board8nintendo2nx13KSleepManager33InvalidateDataCacheForResumeEntryEm, "ax", %progbits
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.global _ZN3ams4kern5board8nintendo2nx13KSleepManager33InvalidateDataCacheForResumeEntryEm
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.type _ZN3ams4kern5board8nintendo2nx13KSleepManager33InvalidateDataCacheForResumeEntryEm, %function
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_ZN3ams4kern5board8nintendo2nx13KSleepManager33InvalidateDataCacheForResumeEntryEm:
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/* cpu::DataSynchronizationBarrier(); */
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dsb sy
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/* const u64 level_sel_value = level << 1; */
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lsl x8, x0, #1
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/* cpu::SetCsselrEl1(level_sel_value); */
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msr csselr_el1, x8
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/* cpu::InstructionMemoryBarrier(); */
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isb
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/* CacheSizeIdAccessor ccsidr_el1; */
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mrs x13, ccsidr_el1
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/* const int num_ways = ccsidr_el1.GetAssociativity(); */
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ubfx w10, w13, #3, #0xA
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/* const int line_size = ccsidr_el1.GetLineSize(); */
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and w11, w13, #7
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/* const int num_sets = ccsidr_el1.GetNumberOfSets(); */
|
||||
ubfx w13, w13, #0xD, #0xF
|
||||
|
||||
/* int way = 0; */
|
||||
mov w9, wzr
|
||||
|
||||
/* const u64 set_shift = static_cast<u64>(line_size + 4); */
|
||||
add w11, w11, #4
|
||||
|
||||
/* const u64 way_shift = static_cast<u64>(__builtin_clz(num_ways)); */
|
||||
clz w12, w10
|
||||
|
||||
|
||||
0: /* do { */
|
||||
/* int set = 0; */
|
||||
mov w14, wzr
|
||||
|
||||
/* const u64 way_value = (static_cast<u64>(way) << way_shift); */
|
||||
lsl w15, w9, w12
|
||||
|
||||
1: /* do { */
|
||||
|
||||
/* const u64 isw_value = (static_cast<u64>(set) << set_shift) | way_value | level_sel_value; */
|
||||
lsl w16, w14, w11
|
||||
orr w16, w16, w15
|
||||
sxtw x16, w16
|
||||
orr x16, x16, x8
|
||||
|
||||
/* __asm__ __volatile__("dc isw, %0" :: "r"(isw_value) : "memory"); */
|
||||
dc isw, x16
|
||||
|
||||
/* while (set <= num_sets); */
|
||||
cmp w13, w14
|
||||
add w14, w14, #1
|
||||
b.ne 1b
|
||||
|
||||
/* while (way <= num_ways); */
|
||||
cmp w9, w10
|
||||
add w9, w9, #1
|
||||
b.ne 0b
|
||||
|
||||
/* cpu::EnsureInstructionConsistency(); */
|
||||
dsb sy
|
||||
isb
|
||||
/* Return. */
|
||||
ret
|
||||
|
|
|
|||
|
|
@ -382,7 +382,7 @@ namespace ams::kern::board::nintendo::nx {
|
|||
return static_cast<u8>((value >> 32) & 0xFF);
|
||||
}
|
||||
|
||||
void KSystemControl::Init::CpuOn(u64 core_id, uintptr_t entrypoint, uintptr_t arg) {
|
||||
void KSystemControl::Init::CpuOnImpl(u64 core_id, uintptr_t entrypoint, uintptr_t arg) {
|
||||
MESOSPHERE_INIT_ABORT_UNLESS((::ams::kern::arch::arm64::smc::CpuOn<smc::SmcId_Supervisor, false>(core_id, entrypoint, arg)) == 0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -395,7 +395,7 @@ namespace ams::kern::board::nintendo::nx::lps {
|
|||
R_SUCCEED();
|
||||
}
|
||||
|
||||
void InvokeCpuSleepHandler(uintptr_t arg, uintptr_t entry) {
|
||||
void InvokeCpuSleepHandler(uintptr_t arg, uintptr_t entry, uintptr_t entry_arg) {
|
||||
/* Verify that we're allowed to perform suspension. */
|
||||
MESOSPHERE_ABORT_UNLESS(g_lps_init_done);
|
||||
MESOSPHERE_ABORT_UNLESS(GetCurrentCoreId() == 0);
|
||||
|
|
@ -416,7 +416,7 @@ namespace ams::kern::board::nintendo::nx::lps {
|
|||
Read(g_pmc_address + APBDEV_PMC_SCRATCH0);
|
||||
|
||||
/* Invoke the sleep hander. */
|
||||
KSleepManager::CpuSleepHandler(arg, entry);
|
||||
KSleepManager::CpuSleepHandler(arg, entry, entry_arg);
|
||||
|
||||
/* Disable deep power down. */
|
||||
Write(g_pmc_address + APBDEV_PMC_DPD_ENABLE, 0);
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ namespace ams::kern::board::nintendo::nx {
|
|||
|
||||
void Initialize();
|
||||
Result EnableSuspend(bool enable);
|
||||
void InvokeCpuSleepHandler(uintptr_t arg, uintptr_t entry);
|
||||
void InvokeCpuSleepHandler(uintptr_t arg, uintptr_t entry, uintptr_t entry_arg);
|
||||
void ResumeBpmpFirmware();
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,6 +20,13 @@
|
|||
|
||||
namespace ams::kern {
|
||||
|
||||
namespace init {
|
||||
|
||||
/* TODO: Is this function name architecture specific? */
|
||||
void StartOtherCore(const ams::kern::init::KInitArguments *init_args);
|
||||
|
||||
}
|
||||
|
||||
/* Initialization. */
|
||||
size_t KSystemControlBase::Init::GetRealMemorySize() {
|
||||
return ams::kern::MainMemorySize;
|
||||
|
|
@ -68,7 +75,7 @@ namespace ams::kern {
|
|||
return 0;
|
||||
}
|
||||
|
||||
void KSystemControlBase::Init::CpuOn(u64 core_id, uintptr_t entrypoint, uintptr_t arg) {
|
||||
void KSystemControlBase::Init::CpuOnImpl(u64 core_id, uintptr_t entrypoint, uintptr_t arg) {
|
||||
#if defined(ATMOSPHERE_ARCH_ARM64)
|
||||
MESOSPHERE_INIT_ABORT_UNLESS((::ams::kern::arch::arm64::smc::CpuOn<0, false>(core_id, entrypoint, arg)) == 0);
|
||||
#else
|
||||
|
|
@ -76,6 +83,22 @@ namespace ams::kern {
|
|||
#endif
|
||||
}
|
||||
|
||||
void KSystemControlBase::Init::TurnOnCpu(u64 core_id, const ams::kern::init::KInitArguments *args) {
|
||||
/* Get entrypoint. */
|
||||
KPhysicalAddress entrypoint = Null<KPhysicalAddress>;
|
||||
while (!cpu::GetPhysicalAddressReadable(std::addressof(entrypoint), reinterpret_cast<uintptr_t>(::ams::kern::init::StartOtherCore), true)) { /* ... */ }
|
||||
|
||||
/* Get arguments. */
|
||||
KPhysicalAddress args_addr = Null<KPhysicalAddress>;
|
||||
while (!cpu::GetPhysicalAddressReadable(std::addressof(args_addr), reinterpret_cast<uintptr_t>(args), true)) { /* ... */ }
|
||||
|
||||
/* Ensure cache is correct for the initial arguments. */
|
||||
cpu::StoreDataCacheForInitArguments(args, sizeof(*args));
|
||||
|
||||
/* Turn on the cpu. */
|
||||
KSystemControl::Init::CpuOnImpl(core_id, GetInteger(entrypoint), GetInteger(args_addr));
|
||||
}
|
||||
|
||||
/* Randomness for Initialization. */
|
||||
void KSystemControlBase::Init::GenerateRandom(u64 *dst, size_t count) {
|
||||
if (AMS_UNLIKELY(!s_initialized_random_generator)) {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue