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https://github.com/Atmosphere-NX/Atmosphere.git
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exo2: implement SmcGetConfig
This commit is contained in:
Michael Scire
SciresM
parent
e3eadcd2e3
commit
6bf283ec2e
15 changed files with 640 additions and 45 deletions
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@ -20,6 +20,11 @@ namespace ams::fuse {
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namespace {
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struct OdmWord2 {
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using DeviceUniqueKeyGeneration = util::BitPack32::Field<0, 5, int>;
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using Reserved = util::BitPack32::Field<5, 27, int>;
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};
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struct OdmWord4 {
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using HardwareState1 = util::BitPack32::Field<0, 2, int>;
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using HardwareType1 = util::BitPack32::Field<HardwareState1::Next, 1, int>;
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@ -52,6 +57,9 @@ namespace ams::fuse {
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constinit uintptr_t g_register_address = secmon::MemoryRegionPhysicalDeviceFuses.GetAddress();
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constinit bool g_checked_for_rcm_bug_patch = false;
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constinit bool g_has_rcm_bug_patch = false;
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ALWAYS_INLINE volatile FuseRegisterRegion *GetRegisterRegion() {
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return reinterpret_cast<volatile FuseRegisterRegion *>(g_register_address);
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}
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@ -64,6 +72,92 @@ namespace ams::fuse {
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return GetRegisterRegion()->chip;
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}
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bool IsIdle() {
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return reg::HasValue(GetRegisters().FUSE_FUSECTRL, FUSE_REG_BITS_ENUM(FUSECTRL_STATE, IDLE));
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}
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void WaitForIdle() {
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while (!IsIdle()) { /* ... */ }
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}
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bool IsNewFuseFormat() {
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/* On mariko, this should always be true. */
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if (GetSocType() != SocType_Erista) {
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return true;
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}
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/* Require that the format version be non-zero in odm4. */
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if (util::BitPack32{GetOdmWord(4)}.Get<OdmWord4::FormatVersion>() == 0) {
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return false;
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}
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/* Check that odm word 0/1 are fused with the magic values. */
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constexpr u32 NewFuseFormatMagic0 = 0x8E61ECAE;
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constexpr u32 NewFuseFormatMagic1 = 0xF2BA3BB2;
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const u32 w0 = GetOdmWord(0);
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const u32 w1 = GetOdmWord(1);
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return w0 == NewFuseFormatMagic0 && w1 == NewFuseFormatMagic1;
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}
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constexpr u32 CompressLotCode(u32 lot0) {
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constexpr int Radix = 36;
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constexpr int Count = 5;
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constexpr int Width = 6;
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constexpr u32 Mask = (1u << Width) - 1;
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u32 compressed = 0;
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for (int i = Count - 1; i >= 0; --i) {
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compressed *= Radix;
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compressed += (lot0 >> (i * Width)) & Mask;
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}
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return compressed;
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}
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constexpr const TargetFirmware FuseVersionIncrementFirmwares[] = {
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TargetFirmware_10_0_0,
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TargetFirmware_9_1_0,
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TargetFirmware_9_0_0,
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TargetFirmware_8_1_0,
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TargetFirmware_7_0_0,
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TargetFirmware_6_2_0,
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TargetFirmware_6_0_0,
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TargetFirmware_5_0_0,
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TargetFirmware_4_0_0,
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TargetFirmware_3_0_2,
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TargetFirmware_3_0_0,
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TargetFirmware_2_0_0,
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TargetFirmware_1_0_0,
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};
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constexpr inline int NumFuseIncrements = util::size(FuseVersionIncrementFirmwares);
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/* Verify that the fuse version increment list is sorted. */
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static_assert([] {
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for (size_t i = 0; i < util::size(FuseVersionIncrementFirmwares) - 1; ++i) {
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if (FuseVersionIncrementFirmwares[i] <= FuseVersionIncrementFirmwares[i + 1]) {
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return false;
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}
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}
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return true;
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}());
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constexpr int GetExpectedFuseVersionImpl(TargetFirmware target_fw) {
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for (int i = 0; i < NumFuseIncrements; ++i) {
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if (target_fw >= FuseVersionIncrementFirmwares[i]) {
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return NumFuseIncrements - i;
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}
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}
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return 0;
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}
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static_assert(GetExpectedFuseVersionImpl(TargetFirmware_10_0_0) == 13);
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static_assert(GetExpectedFuseVersionImpl(TargetFirmware_1_0_0) == 1);
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static_assert(GetExpectedFuseVersionImpl(static_cast<TargetFirmware>(0)) == 0);
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}
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void SetRegisterAddress(uintptr_t address) {
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@ -78,10 +172,84 @@ namespace ams::fuse {
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reg::Write(GetRegisters().FUSE_DISABLEREGPROGRAM, FUSE_REG_BITS_ENUM(DISABLEREGPROGRAM_DISABLEREGPROGRAM_VAL, ENABLE));
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}
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u32 ReadWord(int address) {
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/* Require that the fuse array be idle. */
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AMS_ABORT_UNLESS(IsIdle());
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/* Get the registers. */
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volatile auto &FUSE = GetRegisters();
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/* Write the address to read. */
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reg::Write(FUSE.FUSE_FUSEADDR, address);
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/* Set control to read. */
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reg::ReadWrite(FUSE.FUSE_FUSECTRL, FUSE_REG_BITS_ENUM(FUSECTRL_CMD, READ));
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/* Wait 1 us. */
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util::WaitMicroSeconds(1);
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/* Wait for the array to be idle. */
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WaitForIdle();
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return reg::Read(FUSE.FUSE_FUSERDATA);
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}
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u32 GetOdmWord(int index) {
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return GetChipRegisters().FUSE_RESERVED_ODM[index];
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}
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void GetEcid(br::BootEcid *out) {
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/* Get the registers. */
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const volatile auto &chip = GetChipRegisters();
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/* Read the ecid components. */
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const u32 vendor = reg::Read(chip.FUSE_OPT_VENDOR_CODE) & ((1u << 4) - 1);
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const u32 fab = reg::Read(chip.FUSE_OPT_FAB_CODE) & ((1u << 6) - 1);
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const u32 lot0 = reg::Read(chip.FUSE_OPT_LOT_CODE_0) /* all 32 bits */ ;
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const u32 lot1 = reg::Read(chip.FUSE_OPT_LOT_CODE_1) & ((1u << 28) - 1);
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const u32 wafer = reg::Read(chip.FUSE_OPT_WAFER_ID) & ((1u << 6) - 1);
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const u32 x_coord = reg::Read(chip.FUSE_OPT_X_COORDINATE) & ((1u << 9) - 1);
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const u32 y_coord = reg::Read(chip.FUSE_OPT_Y_COORDINATE) & ((1u << 9) - 1);
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const u32 reserved = reg::Read(chip.FUSE_OPT_OPS_RESERVED) & ((1u << 6) - 1);
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/* Clear the output. */
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util::ClearMemory(out, sizeof(*out));
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/* Copy the component bits. */
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out->ecid[0] = static_cast<u32>((lot1 << 30) | (wafer << 24) | (x_coord << 15) | (y_coord << 6) | (reserved));
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out->ecid[1] = static_cast<u32>((lot0 << 26) | (lot1 >> 2));
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out->ecid[2] = static_cast<u32>((fab << 26) | (lot0 >> 6));
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out->ecid[3] = static_cast<u32>(vendor);
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}
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u64 GetDeviceId() {
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/* Get the registers. */
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const volatile auto &chip = GetChipRegisters();
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/* Read the device id components. */
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/* NOTE: Device ID is "basically" just an alternate encoding of Ecid. */
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/* It elides lot1 (and compresses lot0), but this is fine because */
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/* lot1 is fixed-value for all fused devices. */
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const u64 fab = reg::Read(chip.FUSE_OPT_FAB_CODE) & ((1u << 6) - 1);
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const u32 lot0 = reg::Read(chip.FUSE_OPT_LOT_CODE_0) /* all 32 bits */ ;
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const u64 wafer = reg::Read(chip.FUSE_OPT_WAFER_ID) & ((1u << 6) - 1);
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const u64 x_coord = reg::Read(chip.FUSE_OPT_X_COORDINATE) & ((1u << 9) - 1);
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const u64 y_coord = reg::Read(chip.FUSE_OPT_Y_COORDINATE) & ((1u << 9) - 1);
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/* Compress lot0 down from 32-bits to 26. */
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const u64 clot0 = CompressLotCode(lot0) & ((1u << 26) - 1);
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return (y_coord << 0) |
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(x_coord << 9) |
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(wafer << 18) |
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(clot0 << 24) |
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(fab << 50);
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}
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DramId GetDramId() {
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return static_cast<DramId>(util::BitPack32{GetOdmWord(4)}.Get<OdmWord4::DramId>());
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}
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HardwareType GetHardwareType() {
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/* Read the odm word. */
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const util::BitPack32 odm_word4 = { GetOdmWord(4) };
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@ -113,33 +281,85 @@ namespace ams::fuse {
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}
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}
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QuestState GetQuestState() {
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return static_cast<QuestState>(util::BitPack32{GetOdmWord(4)}.Get<OdmWord4::QuestState>());
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}
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pmic::Regulator GetRegulator() {
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/* TODO: How should mariko be handled? This reads from ODM word 28 in fuses (not presesnt in erista...). */
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/* TODO: How should mariko be handled? This reads from ODM word 28 in fuses (not present in erista...). */
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return pmic::Regulator_Erista_Max77621;
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}
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void GetEcid(br::BootEcid *out) {
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/* Get the registers. */
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const volatile auto &chip = GetChipRegisters();
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int GetDeviceUniqueKeyGeneration() {
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if (IsNewFuseFormat()) {
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return util::BitPack32{GetOdmWord(2)}.Get<OdmWord2::DeviceUniqueKeyGeneration>();
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} else {
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return 0;
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}
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}
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/* Read the ecid components. */
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const u32 vendor = reg::Read(chip.FUSE_OPT_VENDOR_CODE);
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const u32 fab = reg::Read(chip.FUSE_OPT_FAB_CODE);
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const u32 lot0 = reg::Read(chip.FUSE_OPT_LOT_CODE_0);
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const u32 lot1 = reg::Read(chip.FUSE_OPT_LOT_CODE_1);
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const u32 wafer = reg::Read(chip.FUSE_OPT_WAFER_ID);
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const u32 x_coord = reg::Read(chip.FUSE_OPT_X_COORDINATE);
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const u32 y_coord = reg::Read(chip.FUSE_OPT_Y_COORDINATE);
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const u32 reserved = reg::Read(chip.FUSE_OPT_OPS_RESERVED);
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SocType GetSocType() {
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switch (GetHardwareType()) {
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case HardwareType_Icosa:
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case HardwareType_Copper:
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return SocType_Erista;
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case HardwareType_Iowa:
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case HardwareType_Hoag:
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case HardwareType_Calcio:
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case HardwareType_Five:
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return SocType_Mariko;
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default:
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return SocType_Undefined;
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}
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}
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/* Clear the output. */
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util::ClearMemory(out, sizeof(*out));
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int GetExpectedFuseVersion(TargetFirmware target_fw) {
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return GetExpectedFuseVersionImpl(target_fw);
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}
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/* Copy the component bits. */
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out->ecid[0] = static_cast<u32>((lot1 << 30) | (wafer << 24) | (x_coord << 15) | (y_coord << 6) | (reserved));
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out->ecid[1] = static_cast<u32>((lot0 << 26) | (lot1 >> 2));
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out->ecid[2] = static_cast<u32>((fab << 26) | (lot0 >> 6));
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out->ecid[3] = static_cast<u32>(vendor);
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bool HasRcmVulnerabilityPatch() {
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/* Only check for RCM bug patch once, and cache our result. */
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if (!g_checked_for_rcm_bug_patch) {
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do {
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/* Mariko units are necessarily patched. */
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if (fuse::GetSocType() != SocType_Erista) {
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g_has_rcm_bug_patch = true;
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break;
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}
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/* Some patched units use XUSB in RCM. */
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if (reg::Read(GetChipRegisters().FUSE_RESERVED_SW) & 0x80) {
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g_has_rcm_bug_patch = true;
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break;
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}
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/* Other units have a proper ipatch instead. */
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u32 word_count = reg::Read(GetChipRegisters().FUSE_FIRST_BOOTROM_PATCH_SIZE) & 0x7F;
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u32 word_addr = 191;
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while (word_count && !g_has_rcm_bug_patch) {
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u32 word0 = ReadWord(word_addr);
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u32 ipatch_count = (word0 >> 16) & 0xF;
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for (u32 i = 0; i < ipatch_count && !g_has_rcm_bug_patch; ++i) {
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u32 word = ReadWord(word_addr - (i + 1));
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u32 addr = (word >> 16) * 2;
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if (addr == 0x769a) {
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g_has_rcm_bug_patch = true;
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break;
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}
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}
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word_addr -= word_count;
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word_count = word0 >> 25;
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}
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} while (0);
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g_checked_for_rcm_bug_patch = true;
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}
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return g_has_rcm_bug_patch;
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}
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}
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@ -213,6 +213,31 @@ namespace ams::fuse {
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#define DEFINE_FUSE_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(FUSE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
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#define DEFINE_FUSE_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (FUSE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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DEFINE_FUSE_REG_TWO_BIT_ENUM(FUSECTRL_CMD, 0, IDLE, READ, WRITE, SENSE_CTRL);
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DEFINE_FUSE_REG(FUSECTRL_STATE, 16, 5);
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enum FUSE_FUSECTRL_STATE {
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FUSE_FUSECTRL_STATE_RESET = 0,
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FUSE_FUSECTRL_STATE_POST_RESET = 1,
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FUSE_FUSECTRL_STATE_LOAD_ROW0 = 2,
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FUSE_FUSECTRL_STATE_LOAD_ROW1 = 3,
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FUSE_FUSECTRL_STATE_IDLE = 4,
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FUSE_FUSECTRL_STATE_READ_SETUP = 5,
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FUSE_FUSECTRL_STATE_READ_STROBE = 6,
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FUSE_FUSECTRL_STATE_SAMPLE_FUSES = 7,
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FUSE_FUSECTRL_STATE_READ_HOLD = 8,
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FUSE_FUSECTRL_STATE_FUSE_SRC_SETUP = 9,
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FUSE_FUSECTRL_STATE_WRITE_SETUP = 10,
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FUSE_FUSECTRL_STATE_WRITE_ADDR_SETUP = 11,
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FUSE_FUSECTRL_STATE_WRITE_PROGRAM = 12,
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FUSE_FUSECTRL_STATE_WRITE_ADDR_HOLD = 13,
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FUSE_FUSECTRL_STATE_FUSE_SRC_HOLD = 14,
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FUSE_FUSECTRL_STATE_LOAD_RIR = 15,
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FUSE_FUSECTRL_STATE_READ_BEFORE_WRITE_SETUP = 16,
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FUSE_FUSECTRL_STATE_READ_DEASSERT_PD = 17,
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};
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DEFINE_FUSE_REG_BIT_ENUM(PRIVATEKEYDISABLE_TZ_STICKY_BIT_VAL, 4, KEY_VISIBLE, KEY_INVISIBLE);
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DEFINE_FUSE_REG_BIT_ENUM(PRIVATEKEYDISABLE_PRIVATEKEYDISABLE_VAL_KEY, 0, VISIBLE, INVISIBLE);
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