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https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-05-24 03:36:52 -04:00
fusee-cpp: implement SecureInitialize besides InitializeClock()
This commit is contained in:
Michael Scire
SciresM
parent
c9bd97192f
commit
669564b022
10 changed files with 314 additions and 115 deletions
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@ -21,108 +21,112 @@
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#include <vapours/results.hpp>
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#include <vapours/reg.hpp>
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#define APBDEV_PMC_CNTRL (0x000)
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#define APBDEV_PMC_WAKE_MASK (0x00C)
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#define APBDEV_PMC_WAKE_LVL (0x010)
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#define APBDEV_PMC_WAKE_STATUS (0x014)
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#define APBDEV_PMC_DPD_PADS_ORIDE (0x01C)
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#define APBDEV_PMC_DPD_SAMPLE (0x020)
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#define APBDEV_PMC_DPD_ENABLE (0x024)
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#define APBDEV_PMC_CLAMP_STATUS (0x02C)
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#define APBDEV_PMC_PWRGATE_TOGGLE (0x030)
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#define APBDEV_PMC_REMOVE_CLAMPING_CMD (0x034)
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#define APBDEV_PMC_PWRGATE_STATUS (0x038)
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#define APBDEV_PMC_PWRGOOD_TIMER (0x03C)
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#define APBDEV_PMC_BLINK_TIMER (0x040)
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#define APBDEV_PMC_NO_IOPOWER (0x044)
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#define APBDEV_PMC_PWR_DET (0x048)
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#define APBDEV_PMC_SCRATCH0 (0x050)
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#define APBDEV_PMC_SCRATCH1 (0x054)
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#define APBDEV_PMC_SCRATCH4 (0x060)
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#define APBDEV_PMC_SCRATCH12 (0x080)
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#define APBDEV_PMC_SCRATCH13 (0x084)
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#define APBDEV_PMC_SCRATCH18 (0x098)
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#define APBDEV_PMC_SCRATCH20 (0x0A0)
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#define APBDEV_PMC_AUTO_WAKE_LVL_MASK (0x0DC)
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#define APBDEV_PMC_WAKE_DELAY (0x0E0)
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#define APBDEV_PMC_PWR_DET_VAL (0x0E4)
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#define APBDEV_PMC_CRYPTO_OP (0x0F4)
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#define APBDEV_PMC_SCRATCH31 (0x118)
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#define APBDEV_PMC_SCRATCH32 (0x11C)
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#define APBDEV_PMC_SCRATCH33 (0x120)
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#define APBDEV_PMC_SCRATCH39 (0x138)
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#define APBDEV_PMC_SCRATCH40 (0x13C)
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#define APBDEV_PMC_WAKE2_MASK (0x160)
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#define APBDEV_PMC_WAKE2_LVL (0x164)
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#define APBDEV_PMC_WAKE2_STATUS (0x168)
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#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170)
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#define APBDEV_PMC_OSC_EDPD_OVER (0x1A4)
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#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8)
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#define APBDEV_PMC_RST_STATUS (0x1B4)
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#define APBDEV_PMC_IO_DPD_REQ (0x1B8)
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#define APBDEV_PMC_IO_DPD_STATUS (0x1BC)
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#define APBDEV_PMC_IO_DPD2_REQ (0x1C0)
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#define APBDEV_PMC_IO_DPD2_STATUS (0x1C4)
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#define APBDEV_PMC_SEL_DPD_TIM (0x1C8)
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#define APBDEV_PMC_SCRATCH45 (0x234)
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#define APBDEV_PMC_SCRATCH46 (0x238)
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#define APBDEV_PMC_SCRATCH49 (0x244)
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#define APBDEV_PMC_TSC_MULT (0x2B4)
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#define APBDEV_PMC_STICKY_BITS (0x2C0)
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#define APBDEV_PMC_WEAK_BIAS (0x2C8)
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#define APBDEV_PMC_GPU_RG_CNTRL (0x2D4)
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#define APBDEV_PMC_CNTRL2 (0x440)
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#define APBDEV_PMC_FUSE_CTRL (0x450)
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#define APBDEV_PMC_IO_DPD3_REQ (0x45C)
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#define APBDEV_PMC_IO_DPD3_STATUS (0x460)
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#define APBDEV_PMC_IO_DPD4_REQ (0x464)
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#define APBDEV_PMC_IO_DPD4_STATUS (0x468)
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#define APBDEV_PMC_SET_SW_CLAMP (0x47C)
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#define APBDEV_PMC_WAKE_DEBOUNCE_EN (0x4D8)
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#define APBDEV_PMC_DDR_CNTRL (0x4E4)
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#define APBDEV_PMC_SEC_DISABLE (0x004)
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#define APBDEV_PMC_SEC_DISABLE2 (0x2C4)
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#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
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#define APBDEV_PMC_SEC_DISABLE4 (0x5B0)
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#define APBDEV_PMC_SEC_DISABLE5 (0x5B4)
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#define APBDEV_PMC_SEC_DISABLE6 (0x5B8)
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#define APBDEV_PMC_SEC_DISABLE7 (0x5BC)
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#define APBDEV_PMC_SEC_DISABLE8 (0x5C0)
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#define APBDEV_PMC_SCRATCH43 (0x22C)
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#define APBDEV_PMC_SCRATCH190 (0x818)
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#define APBDEV_PMC_SCRATCH200 (0x840)
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#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
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#define APBDEV_PMC_SECURE_SCRATCH4 (0x0C0)
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#define APBDEV_PMC_SECURE_SCRATCH5 (0x0C4)
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#define APBDEV_PMC_SECURE_SCRATCH6 (0x224)
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#define APBDEV_PMC_SECURE_SCRATCH7 (0x228)
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#define APBDEV_PMC_SECURE_SCRATCH16 (0x320)
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#define APBDEV_PMC_SECURE_SCRATCH21 (0x334)
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#define APBDEV_PMC_SECURE_SCRATCH24 (0x340)
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#define APBDEV_PMC_SECURE_SCRATCH25 (0x344)
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#define APBDEV_PMC_SECURE_SCRATCH26 (0x348)
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#define APBDEV_PMC_SECURE_SCRATCH27 (0x34C)
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#define APBDEV_PMC_SECURE_SCRATCH32 (0x360)
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#define APBDEV_PMC_SECURE_SCRATCH34 (0x368)
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#define APBDEV_PMC_SECURE_SCRATCH35 (0x36C)
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#define APBDEV_PMC_SECURE_SCRATCH39 (0x37C)
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#define APBDEV_PMC_SECURE_SCRATCH51 (0x3AC)
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#define APBDEV_PMC_SECURE_SCRATCH55 (0x3BC)
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#define APBDEV_PMC_SECURE_SCRATCH74 (0x408)
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#define APBDEV_PMC_SECURE_SCRATCH75 (0x40C)
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#define APBDEV_PMC_SECURE_SCRATCH76 (0x410)
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#define APBDEV_PMC_SECURE_SCRATCH77 (0x414)
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#define APBDEV_PMC_SECURE_SCRATCH78 (0x418)
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#define APBDEV_PMC_SECURE_SCRATCH99 (0xAE4)
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#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8)
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#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC)
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#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0)
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#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4)
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#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18)
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#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C)
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#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20)
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#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24)
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#define APBDEV_PMC_SECURE_SCRATCH119 (0xB34)
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#define APBDEV_PMC_CNTRL (0x000)
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#define APBDEV_PMC_WAKE_MASK (0x00C)
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#define APBDEV_PMC_WAKE_LVL (0x010)
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#define APBDEV_PMC_WAKE_STATUS (0x014)
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#define APBDEV_PMC_DPD_PADS_ORIDE (0x01C)
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#define APBDEV_PMC_DPD_SAMPLE (0x020)
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#define APBDEV_PMC_DPD_ENABLE (0x024)
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#define APBDEV_PMC_CLAMP_STATUS (0x02C)
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#define APBDEV_PMC_PWRGATE_TOGGLE (0x030)
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#define APBDEV_PMC_REMOVE_CLAMPING_CMD (0x034)
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#define APBDEV_PMC_PWRGATE_STATUS (0x038)
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#define APBDEV_PMC_PWRGOOD_TIMER (0x03C)
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#define APBDEV_PMC_BLINK_TIMER (0x040)
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#define APBDEV_PMC_NO_IOPOWER (0x044)
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#define APBDEV_PMC_PWR_DET (0x048)
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#define APBDEV_PMC_SCRATCH0 (0x050)
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#define APBDEV_PMC_SCRATCH1 (0x054)
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#define APBDEV_PMC_SCRATCH4 (0x060)
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#define APBDEV_PMC_SCRATCH12 (0x080)
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#define APBDEV_PMC_SCRATCH13 (0x084)
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#define APBDEV_PMC_SCRATCH18 (0x098)
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#define APBDEV_PMC_SCRATCH20 (0x0A0)
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#define APBDEV_PMC_AUTO_WAKE_LVL_MASK (0x0DC)
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#define APBDEV_PMC_WAKE_DELAY (0x0E0)
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#define APBDEV_PMC_PWR_DET_VAL (0x0E4)
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#define APBDEV_PMC_CRYPTO_OP (0x0F4)
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#define APBDEV_PMC_SCRATCH31 (0x118)
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#define APBDEV_PMC_SCRATCH32 (0x11C)
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#define APBDEV_PMC_SCRATCH33 (0x120)
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#define APBDEV_PMC_SCRATCH39 (0x138)
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#define APBDEV_PMC_SCRATCH40 (0x13C)
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#define APBDEV_PMC_WAKE2_MASK (0x160)
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#define APBDEV_PMC_WAKE2_LVL (0x164)
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#define APBDEV_PMC_WAKE2_STATUS (0x168)
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#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170)
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#define APBDEV_PMC_OSC_EDPD_OVER (0x1A4)
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#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8)
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#define APBDEV_PMC_RST_STATUS (0x1B4)
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#define APBDEV_PMC_IO_DPD_REQ (0x1B8)
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#define APBDEV_PMC_IO_DPD_STATUS (0x1BC)
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#define APBDEV_PMC_IO_DPD2_REQ (0x1C0)
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#define APBDEV_PMC_IO_DPD2_STATUS (0x1C4)
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#define APBDEV_PMC_SEL_DPD_TIM (0x1C8)
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#define APBDEV_PMC_SCRATCH45 (0x234)
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#define APBDEV_PMC_SCRATCH46 (0x238)
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#define APBDEV_PMC_SCRATCH49 (0x244)
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#define APBDEV_PMC_TSC_MULT (0x2B4)
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#define APBDEV_PMC_STICKY_BITS (0x2C0)
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#define APBDEV_PMC_WEAK_BIAS (0x2C8)
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#define APBDEV_PMC_GPU_RG_CNTRL (0x2D4)
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#define APBDEV_PMC_CNTRL2 (0x440)
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#define APBDEV_PMC_FUSE_CTRL (0x450)
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#define APBDEV_PMC_IO_DPD3_REQ (0x45C)
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#define APBDEV_PMC_IO_DPD3_STATUS (0x460)
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#define APBDEV_PMC_IO_DPD4_REQ (0x464)
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#define APBDEV_PMC_IO_DPD4_STATUS (0x468)
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#define APBDEV_PMC_SET_SW_CLAMP (0x47C)
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#define APBDEV_PMC_WAKE_DEBOUNCE_EN (0x4D8)
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#define APBDEV_PMC_DDR_CNTRL (0x4E4)
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#define APBDEV_PMC_SEC_DISABLE (0x004)
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#define APBDEV_PMC_SEC_DISABLE2 (0x2C4)
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#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
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#define APBDEV_PMC_SEC_DISABLE4 (0x5B0)
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#define APBDEV_PMC_SEC_DISABLE5 (0x5B4)
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#define APBDEV_PMC_SEC_DISABLE6 (0x5B8)
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#define APBDEV_PMC_SEC_DISABLE7 (0x5BC)
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#define APBDEV_PMC_SEC_DISABLE8 (0x5C0)
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#define APBDEV_PMC_SCRATCH43 (0x22C)
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#define APBDEV_PMC_SCRATCH190 (0x818)
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#define APBDEV_PMC_SCRATCH200 (0x840)
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#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
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#define APBDEV_PMC_SECURE_SCRATCH4 (0x0C0)
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#define APBDEV_PMC_SECURE_SCRATCH5 (0x0C4)
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#define APBDEV_PMC_SECURE_SCRATCH6 (0x224)
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#define APBDEV_PMC_SECURE_SCRATCH7 (0x228)
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#define APBDEV_PMC_SECURE_SCRATCH16 (0x320)
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#define APBDEV_PMC_SECURE_SCRATCH21 (0x334)
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#define APBDEV_PMC_SECURE_SCRATCH24 (0x340)
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#define APBDEV_PMC_SECURE_SCRATCH25 (0x344)
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#define APBDEV_PMC_SECURE_SCRATCH26 (0x348)
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#define APBDEV_PMC_SECURE_SCRATCH27 (0x34C)
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#define APBDEV_PMC_SECURE_SCRATCH32 (0x360)
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#define APBDEV_PMC_SECURE_SCRATCH34 (0x368)
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#define APBDEV_PMC_SECURE_SCRATCH35 (0x36C)
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#define APBDEV_PMC_SECURE_SCRATCH39 (0x37C)
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#define APBDEV_PMC_SECURE_SCRATCH51 (0x3AC)
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#define APBDEV_PMC_SECURE_SCRATCH55 (0x3BC)
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#define APBDEV_PMC_SECURE_SCRATCH74 (0x408)
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#define APBDEV_PMC_SECURE_SCRATCH75 (0x40C)
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#define APBDEV_PMC_SECURE_SCRATCH76 (0x410)
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#define APBDEV_PMC_SECURE_SCRATCH77 (0x414)
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#define APBDEV_PMC_SECURE_SCRATCH78 (0x418)
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#define APBDEV_PMC_SECURE_SCRATCH99 (0xAE4)
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#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8)
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#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC)
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#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0)
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#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4)
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#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18)
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#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C)
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#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20)
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#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24)
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#define APBDEV_PMC_SECURE_SCRATCH119 (0xB34)
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#define APBDEV_PMC_TZRAM_PWR_CNTRL (0xBE8)
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#define APBDEV_PMC_TZRAM_SEC_DISABLE (0xBEC)
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#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE (0xBF0)
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#define PMC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (APBDEV_PMC, NAME)
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@ -247,3 +251,12 @@ DEFINE_PMC_REG_BIT_ENUM(STICKY_BITS_JTAG_STS, 6, ENABLE, DISABLE);
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DEFINE_PMC_REG_BIT_ENUM(CNTRL2_WAKE_DET_EN, 9, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(SEC_DISABLE2_WRITE21, 26, OFF, ON);
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DEFINE_PMC_REG(TZRAM_PWR_CNTRL_TZRAM_SD, 0, 1);
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DEFINE_PMC_REG(TZRAM_PWR_CNTRL_TZRAM_SLCG_OVR, 1, 1);
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DEFINE_PMC_REG_BIT_ENUM(TZRAM_SEC_DISABLE_SD_WRITE, 0, OFF, ON);
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DEFINE_PMC_REG_BIT_ENUM(TZRAM_SEC_DISABLE_SD_READ, 1, OFF, ON);
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DEFINE_PMC_REG_BIT_ENUM(TZRAM_NON_SEC_DISABLE_SD_WRITE, 0, OFF, ON);
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DEFINE_PMC_REG_BIT_ENUM(TZRAM_NON_SEC_DISABLE_SD_READ, 1, OFF, ON);
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