mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-05-16 08:04:23 -04:00
fusee_cpp: various fixes, unpatched erista boots now
This commit is contained in:
Michael Scire
SciresM
parent
e5106ffa2c
commit
596f5c3f52
8 changed files with 1032 additions and 68 deletions
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@ -76,14 +76,14 @@ namespace ams::nxboot {
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switch (index) {
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case 0:
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case 3:
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std::memcpy(mtc_tables_buffer, T210SdevEmcDvfsTableS4gb01, sizeof(T210SdevEmcDvfsTableS4gb01));
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return reinterpret_cast<EmcDvfsTimingTable *>(mtc_tables_buffer);
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//std::memcpy(mtc_tables_buffer, T210SdevEmcDvfsTableS4gb01, sizeof(T210SdevEmcDvfsTableS4gb01));
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return reinterpret_cast<EmcDvfsTimingTable *>(const_cast<u8 *>(T210SdevEmcDvfsTableS4gb01));
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case 1:
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std::memcpy(mtc_tables_buffer, T210SdevEmcDvfsTableS6gb01, sizeof(T210SdevEmcDvfsTableS6gb01));
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return reinterpret_cast<EmcDvfsTimingTable *>(mtc_tables_buffer);
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//std::memcpy(mtc_tables_buffer, T210SdevEmcDvfsTableS6gb01, sizeof(T210SdevEmcDvfsTableS6gb01));
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return reinterpret_cast<EmcDvfsTimingTable *>(const_cast<u8 *>(T210SdevEmcDvfsTableS6gb01));
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case 2:
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std::memcpy(mtc_tables_buffer, T210SdevEmcDvfsTableH4gb01, sizeof(T210SdevEmcDvfsTableH4gb01));
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return reinterpret_cast<EmcDvfsTimingTable *>(mtc_tables_buffer);
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//std::memcpy(mtc_tables_buffer, T210SdevEmcDvfsTableH4gb01, sizeof(T210SdevEmcDvfsTableH4gb01));
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return reinterpret_cast<EmcDvfsTimingTable *>(const_cast<u8 *>(T210SdevEmcDvfsTableH4gb01));
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default:
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ShowFatalError("Unknown EmcDvfsTimingTableIndex: %d\n", index);
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}
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@ -153,14 +153,19 @@ namespace ams::nxboot {
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u32 ProgramPllm(u32 next_rate_khz, u32 next_clk_src, bool is_pllmb) {
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/* Hardcode values for 1600MHz. */
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if (next_rate_khz != 1600000) {
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u32 divn, divm, divp;
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if (next_rate_khz == 1600000) {
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divn = 0x7D;
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divm = 0x03;
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divp = 0x00;
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} else if (next_rate_khz == 800000) {
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divn = 0x7D;
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divm = 0x03;
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divp = 0x01;
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} else {
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ShowFatalError("Unexpected ProgramPllm next rate %" PRIu32 "\n", next_rate_khz);
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}
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const u32 divn = 0x7D;
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const u32 divm = 0x03;
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const u32 divp = 0x00;
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const auto next_2x = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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if (is_pllmb) {
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/* Set divisors. */
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@ -2712,48 +2717,6 @@ namespace ams::nxboot {
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}
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}
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void Dvfs(EmcDvfsTimingTable *dst_timing, EmcDvfsTimingTable *src_timing, bool train) {
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/* Get the old 2x clock source. */
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const u32 prev_2x_clk_src = reg::GetValue(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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/* Set g_next_pll. */
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g_next_pll = prev_2x_clk_src == PLLMB_UD || prev_2x_clk_src == PLLMB_OUT0;
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/* Reprogram pll. */
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u32 next_clk_src;
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if (PllReprogram(dst_timing->rate_khz, dst_timing->clk_src_emc, src_timing->rate_khz, src_timing->clk_src_emc)) {
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if (prev_2x_clk_src == PLLMB_UD || prev_2x_clk_src == PLLMB_OUT0) {
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g_next_pll = 0;
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} else if (prev_2x_clk_src == PLLM_UD || prev_2x_clk_src == PLLM_OUT0) {
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g_next_pll = !g_next_pll;
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}
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next_clk_src = ProgramPllm(dst_timing->rate_khz, dst_timing->clk_src_emc, g_next_pll);
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} else {
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next_clk_src = dst_timing->clk_src_emc;
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const u32 next_2x_clk_src = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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if (next_2x_clk_src == PLLM_UD || next_2x_clk_src == PLLMB_UD) {
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if (g_next_pll) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_UD));
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}
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} else if (next_2x_clk_src == PLLM_OUT0 || next_2x_clk_src == PLLMB_OUT0) {
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if (g_next_pll) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_OUT0));
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}
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}
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}
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if (train) {
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TrainFreq(src_timing, dst_timing, next_clk_src);
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if (PllReprogram(dst_timing->rate_khz, dst_timing->clk_src_emc, src_timing->rate_khz, src_timing->clk_src_emc)) {
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g_next_pll = !g_next_pll;
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}
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} else {
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FreqChange(src_timing, dst_timing, 0, next_clk_src);
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}
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}
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constexpr inline const u16 PeriodicCompensationRegisters[] = {
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0,
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1,
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@ -2830,36 +2793,87 @@ namespace ams::nxboot {
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}
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}
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void Dvfs(EmcDvfsTimingTable *dst_timing, EmcDvfsTimingTable *src_timing, bool train) {
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/* Get the old 2x clock source. */
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const u32 prev_2x_clk_src = reg::GetValue(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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/* Set g_next_pll. */
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g_next_pll = prev_2x_clk_src == PLLMB_UD || prev_2x_clk_src == PLLMB_OUT0;
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/* Reprogram pll. */
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u32 next_clk_src;
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if (PllReprogram(dst_timing->rate_khz, dst_timing->clk_src_emc, src_timing->rate_khz, src_timing->clk_src_emc)) {
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if (prev_2x_clk_src == PLLMB_UD || prev_2x_clk_src == PLLMB_OUT0) {
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g_next_pll = 0;
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} else if (prev_2x_clk_src == PLLM_UD || prev_2x_clk_src == PLLM_OUT0) {
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g_next_pll = !g_next_pll;
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}
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next_clk_src = ProgramPllm(dst_timing->rate_khz, dst_timing->clk_src_emc, g_next_pll);
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} else {
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next_clk_src = dst_timing->clk_src_emc;
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const u32 next_2x_clk_src = reg::GetField(next_clk_src, CLK_RST_REG_BITS_MASK(CLK_SOURCE_EMC_EMC_2X_CLK_SRC));
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if (next_2x_clk_src == PLLM_UD || next_2x_clk_src == PLLMB_UD) {
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if (g_next_pll) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_UD));
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}
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} else if (next_2x_clk_src == PLLM_OUT0 || next_2x_clk_src == PLLMB_OUT0) {
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if (g_next_pll) {
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reg::SetField(next_clk_src, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, PLLMB_OUT0));
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}
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}
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}
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if (train) {
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TrainFreq(src_timing, dst_timing, next_clk_src);
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if (PllReprogram(dst_timing->rate_khz, dst_timing->clk_src_emc, src_timing->rate_khz, src_timing->clk_src_emc)) {
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g_next_pll = !g_next_pll;
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}
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} else {
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FreqChange(src_timing, dst_timing, 0, next_clk_src);
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PeriodicCompensationRoutine(dst_timing);
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}
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}
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}
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void DoMemoryTrainingErista(int index, void *mtc_tables_buffer) {
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/* Get timing tables. */
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auto *timing_tables = GetEmcDvfsTimingTables(index, mtc_tables_buffer);
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auto *src_timing = timing_tables + 0;
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auto *dst_timing = timing_tables + 1;
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auto *timing_204 = timing_tables + 0;
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auto *timing_800 = timing_tables + 1;
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auto *timing_1600 = timing_tables + 2;
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/* Check timing tables. */
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if (src_timing->rate_khz != 204000 || dst_timing->rate_khz != 1600000) {
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ShowFatalError("EmcDvfsTimingTables seem corrupted %" PRIu32 " %" PRIu32 "?\n", src_timing->rate_khz, dst_timing->rate_khz);
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if (timing_204->rate_khz != 204000 || timing_1600->rate_khz != 1600000) {
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ShowFatalError("EmcDvfsTimingTables seem corrupted %" PRIu32 " %" PRIu32 " %" PRIu32 "?\n", timing_204->rate_khz, timing_800->rate_khz, timing_1600->rate_khz);
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}
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/* Check that we should do training. */
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if (src_timing->clk_src_emc != reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC)) {
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if (timing_204->clk_src_emc != reg::Read(CLKRST + CLK_RST_CONTROLLER_CLK_SOURCE_EMC)) {
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/* Our clock source isn't what's expected, so presumably training has already been done? */
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/* Either way, the safe bet is to skip it. */
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return;
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}
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/* Train 800MHz. */
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Dvfs(timing_800, timing_204, true);
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/* Train 1600MHz. */
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Dvfs(dst_timing, src_timing, true);
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Dvfs(timing_1600, timing_204, true);
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/* Switch to 800MHz. */
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Dvfs(timing_800, timing_204, false);
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/* Switch to 1600MHz. */
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Dvfs(dst_timing, src_timing, false);
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Dvfs(timing_1600, timing_800, false);
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/* Wait 100ms. */
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util::WaitMicroSeconds(100000);
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/* Do Periodic compensation */
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PeriodicCompensationRoutine(dst_timing);
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util::WaitMicroSeconds(100);
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PeriodicCompensationRoutine(timing_1600);
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}
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}
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