mirrors/Atmosphere
1
0
Fork 0
mirror of https://github.com/Atmosphere-NX/Atmosphere.git synced 2025-06-04 16:53:48 -04:00
Code Issues Projects Releases Packages Wiki Activity

fusee_cpp: implement tsec_keygen firmware execution

Browse source
This commit is contained in:
Michael Scire 2021-08-27 23:20:46 -07:00 • committed by SciresM
parent 80999988d4
commit 51cf28339b
11 changed files with 270 additions and 53 deletions
Download patch file Download diff file Expand all files Collapse all files

156
libraries/libexosphere/source/tsec/tsec_api.cpp
View file

@ -14,46 +14,154 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <exosphere.hpp>
#include "tsec_registers.hpp"
#include "../kfuse/kfuse_registers.hpp"
namespace ams::tsec {
namespace {
enum TsecResult {
constexpr inline const uintptr_t KFUSE = 0x7000FC00;
constexpr inline const uintptr_t TSEC = 0x54500000;
enum TsecResult : u32 {
TsecResult_Success = 0xB0B0B0B0,
TsecResult_Failure = 0xD0D0D0D0,
};
bool RunFirmwareImpl(const void *fw, size_t fw_size) {
/* Enable relevant clocks. */
clkrst::EnableHost1xClock();
clkrst::EnableTsecClock();
clkrst::EnableSorSafeClock();
clkrst::EnableSor0Clock();
clkrst::EnableSor1Clock();
clkrst::EnableKfuseClock();
enum TsecMemory {
TsecMemory_Imem,
TsecMemory_Dmem,
};
/* Disable clocks once we're done. */
ON_SCOPE_EXIT {
clkrst::DisableHost1xClock();
clkrst::DisableTsecClock();
clkrst::DisableSorSafeClock();
clkrst::DisableSor0Clock();
clkrst::DisableSor1Clock();
clkrst::DisableKfuseClock();
};
bool WaitForKfuseReady() {
constexpr auto KfuseTimeout = 10 * 1000; /* 10 ms. */
/* TODO */
AMS_UNUSED(fw, fw_size);
return true;
const u32 end_time = util::GetMicroSeconds() + KfuseTimeout;
/* Wait for STATE_DONE. */
while (!reg::HasValue(KFUSE + KFUSE_STATE, KFUSE_REG_BITS_ENUM(STATE_DONE, DONE))) {
if (util::GetMicroSeconds() >= end_time) {
return false;
}
}
/* Check for STATE_CRCPASS. */
return reg::HasValue(KFUSE + KFUSE_STATE, KFUSE_REG_BITS_ENUM(STATE_CRCPASS, PASS));
}
void WaitForDmaIdle() {
constexpr auto DmaTimeout = 10 * 1000 * 1000; /* 10 Seconds. */
u32 cur_time = util::GetMicroSeconds();
const u32 end_time = cur_time + DmaTimeout;
while (cur_time <= end_time) {
if (reg::HasValue(TSEC + TSEC_FALCON_DMATRFCMD, TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_BUSY, IDLE))) {
return;
}
cur_time = util::GetMicroSeconds();
}
AMS_ABORT("tsec dma timeout");
}
void WaitForTsecIdle() {
constexpr auto TsecTimeout = 2 * 1000 * 1000; /* 2 Seconds. */
u32 cur_time = util::GetMicroSeconds();
const u32 end_time = cur_time + TsecTimeout;
while (cur_time <= end_time) {
if (reg::HasValue(TSEC + TSEC_FALCON_CPUCTL, TSEC_REG_BITS_ENUM(FALCON_CPUCTL_HALTED, TRUE))) {
return;
}
cur_time = util::GetMicroSeconds();
}
AMS_ABORT("tsec timeout");
}
void DoDma256(TsecMemory memory, u32 dst_offset, u32 src_offset) {
reg::Write(TSEC + TSEC_FALCON_DMATRFMOFFS, TSEC_REG_BITS_VALUE(FALCON_DMATRFMOFFS_OFFSET, dst_offset));
reg::Write(TSEC + TSEC_FALCON_DMATRFFBOFFS, src_offset);
if (memory == TsecMemory_Imem) {
reg::Write(TSEC + TSEC_FALCON_DMATRFCMD, TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_TO, IMEM),
TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_SIZE, 4B));
} else {
reg::Write(TSEC + TSEC_FALCON_DMATRFCMD, TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_TO, DMEM),
TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_SIZE, 256B));
}
WaitForDmaIdle();
}
}
bool RunTsecFirmware(const void *fw, size_t fw_size) {
/* TODO */
AMS_UNUSED(fw, fw_size);
return RunFirmwareImpl(fw, fw_size);
/* Enable relevant clocks. */
clkrst::EnableHost1xClock();
clkrst::EnableTsecClock();
clkrst::EnableSorSafeClock();
clkrst::EnableSor0Clock();
clkrst::EnableSor1Clock();
clkrst::EnableKfuseClock();
/* Disable clocks once we're done. */
ON_SCOPE_EXIT {
clkrst::DisableHost1xClock();
clkrst::DisableTsecClock();
clkrst::DisableSorSafeClock();
clkrst::DisableSor0Clock();
clkrst::DisableSor1Clock();
clkrst::DisableKfuseClock();
};
/* Wait for kfuse to be ready. */
if (!WaitForKfuseReady()) {
return false;
}
/* Configure falcon. */
reg::Write(TSEC + TSEC_FALCON_DMACTL, 0);
reg::Write(TSEC + TSEC_FALCON_IRQMSET, 0xFFF2);
reg::Write(TSEC + TSEC_FALCON_IRQDEST, 0xFFF0);
reg::Write(TSEC + TSEC_FALCON_ITFEN, 0x3);
/* Wait for TSEC dma to be idle. */
WaitForDmaIdle();
/* Set the base address for transfers. */
reg::Write(TSEC + TSEC_FALCON_DMATRFBASE, reinterpret_cast<uintptr_t>(fw) >> 8);
/* Transfer all data to TSEC imem. */
for (size_t i = 0; i < fw_size; i += 0x100) {
DoDma256(TsecMemory_Imem, i, i);
}
/* Write the magic value to host1x syncpoint 160. */
reg::Write(0x50003300, 0x34C2E1DA);
/* Execute the firmware. */
reg::Write(TSEC + TSEC_FALCON_MAILBOX0, 0);
reg::Write(TSEC + TSEC_FALCON_MAILBOX1, 0);
reg::Write(TSEC + TSEC_FALCON_BOOTVEC, 0);
reg::Write(TSEC + TSEC_FALCON_CPUCTL, TSEC_REG_BITS_ENUM(FALCON_CPUCTL_STARTCPU, TRUE));
/* Wait for TSEC dma to be idle. */
WaitForDmaIdle();
/* Wait for TSEC to complete. */
WaitForTsecIdle();
/* Clear magic value from host1x syncpoint 160. */
reg::Write(0x50003300, 0);
/* Return whether the tsec firmware succeeded. */
return reg::Read(TSEC + TSEC_FALCON_MAILBOX1) == TsecResult_Success;
}
void Lock() {

49
libraries/libexosphere/source/tsec/tsec_registers.hpp Normal file
View file

@ -0,0 +1,49 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public LicenTSEC,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be uTSECful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOTSEC. TSECe the GNU General Public LicenTSEC for
* more details.
*
* You should have received a copy of the GNU General Public LicenTSEC
* along with this program. If not, TSECe <http://www.gnu.org/licenTSECs/>.
*/
#include <exosphere.hpp>
#define TSEC_FALCON_IRQMSET (0x1010)
#define TSEC_FALCON_IRQDEST (0x101C)
#define TSEC_FALCON_MAILBOX0 (0x1040)
#define TSEC_FALCON_MAILBOX1 (0x1044)
#define TSEC_FALCON_ITFEN (0x1048)
#define TSEC_FALCON_CPUCTL (0x1100)
#define TSEC_FALCON_BOOTVEC (0x1104)
#define TSEC_FALCON_DMACTL (0x110C)
#define TSEC_FALCON_DMATRFBASE (0x1110)
#define TSEC_FALCON_DMATRFMOFFS (0x1114)
#define TSEC_FALCON_DMATRFCMD (0x1118)
#define TSEC_FALCON_DMATRFFBOFFS (0x111C)
#define TSEC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (TSEC, NAME)
#define TSEC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (TSEC, NAME, VALUE)
#define TSEC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (TSEC, NAME, ENUM)
#define TSEC_REG_BITS_ENUM_TSECL(NAME, __COND__, TRUE_ENUM, FALTSEC_ENUM) REG_NAMED_BITS_ENUM_TSECL(TSEC, NAME, __COND__, TRUE_ENUM, FALTSEC_ENUM)
#define DEFINE_TSEC_REG(NAME, __OFFTSECT__, __WIDTH__) REG_DEFINE_NAMED_REG (TSEC, NAME, __OFFTSECT__, __WIDTH__)
#define DEFINE_TSEC_REG_BIT_ENUM(NAME, __OFFTSECT__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (TSEC, NAME, __OFFTSECT__, ZERO, ONE)
#define DEFINE_TSEC_REG_TWO_BIT_ENUM(NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (TSEC, NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE)
#define DEFINE_TSEC_REG_THREE_BIT_ENUM(NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, TSECVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(TSEC, NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, TSECVEN)
#define DEFINE_TSEC_REG_FOUR_BIT_ENUM(NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, TSECVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (TSEC, NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, TSECVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
DEFINE_TSEC_REG_BIT_ENUM(FALCON_CPUCTL_STARTCPU, 1, FALSE, TRUE);
DEFINE_TSEC_REG_BIT_ENUM(FALCON_CPUCTL_HALTED, 4, FALSE, TRUE);
DEFINE_TSEC_REG(FALCON_DMATRFMOFFS_OFFSET, 0, 16);
DEFINE_TSEC_REG_BIT_ENUM(FALCON_DMATRFCMD_BUSY, 1, BUSY, IDLE);
DEFINE_TSEC_REG_BIT_ENUM(FALCON_DMATRFCMD_TO, 4, DMEM, IMEM);
DEFINE_TSEC_REG_THREE_BIT_ENUM(FALCON_DMATRFCMD_SIZE, 8, 4B, 8B, 16B, 32B, 64B, 128B, 256B, RSVD7);