mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-05-29 05:55:16 -04:00
fusee_cpp: implement SDRAM initialization
This commit is contained in:
parent
f2a1c60218
commit
349a16ce39
59 changed files with 4088 additions and 17 deletions
|
@ -41,6 +41,9 @@
|
|||
#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE (0x030)
|
||||
#define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048)
|
||||
#define CLK_RST_CONTROLLER_OSC_CTRL (0x050)
|
||||
#define CLK_RST_CONTROLLER_PLLM_BASE (0x090)
|
||||
#define CLK_RST_CONTROLLER_PLLM_MISC1 (0x098)
|
||||
#define CLK_RST_CONTROLLER_PLLM_MISC2 (0x09C)
|
||||
#define CLK_RST_CONTROLLER_PLLD_BASE (0x0D0)
|
||||
#define CLK_RST_CONTROLLER_PLLD_MISC1 (0x0D8)
|
||||
#define CLK_RST_CONTROLLER_PLLD_MISC (0x0DC)
|
||||
|
@ -92,6 +95,14 @@ DEFINE_CLK_RST_REG_BIT_ENUM(OSC_CTRL_XOE, 0, DISABLE, ENABLE);
|
|||
DEFINE_CLK_RST_REG(OSC_CTRL_XOFS, 4, 6);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(OSC_CTRL_OSC_FREQ, 28, OSC13, OSC16P8, RSVD2, RSVD3, OSC19P2, OSC38P4, RSVD6, RSVD7, OSC12, OSC48, RSVD10, RSVD11, OSC26, RSVD13, RSVD14, RSVD15);
|
||||
|
||||
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVM, 0, 8);
|
||||
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVN, 8, 8);
|
||||
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVP, 20, 5);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_LOCK, 27, NOT_LOCK, LOCK);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_ENABLE, 30, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_BYPASSPLL, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_CSI_CLK_SRC, 23, BRICK, PLL_D);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_ENABLE, 30, DISABLE, ENABLE);
|
||||
|
@ -171,6 +182,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE);
|
|||
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF (0x62C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC (0x630)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 (0x65C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL (0x664)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL (0x66C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM (0x694)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC (0x6A4)
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue