mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-05-22 10:55:14 -04:00
thermosphere: continue vgic rewrite
This commit is contained in:
TuxSH
parent
02bbe1bb40
commit
31e5ff7c1d
4 changed files with 316 additions and 46 deletions
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@ -14,8 +14,11 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <mutex>
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#include "hvisor_virtual_gic.hpp"
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#define GICDOFF(field) (offsetof(GicV2Distributor, field))
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namespace ams::hvisor {
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@ -72,29 +75,6 @@ namespace ams::hvisor {
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);
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}
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VirtualGic::VirqQueue::iterator VirtualGic::VirqQueue::erase(VirtualGic::VirqQueue::iterator startPos, VirtualGic::VirqQueue::iterator endPos)
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{
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VirqState &prev = m_storage[startPos->listPrev];
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VirqState &next = *endPos;
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u32 nextPos = GetStateIndex(*endPos);
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if (startPos->listPrev != virqListEndIndex) {
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prev.listNext = nextPos;
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} else {
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m_first = &next;
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}
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if (nextPos != virqListEndIndex) {
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next.listPrev = startPos->listPrev;
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} else {
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m_last = &prev;
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}
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for (auto it = startPos; it != endPos; ++it) {
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it->listPrev = it->listNext = virqListInvalidIndex;
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}
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}
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void VirtualGic::SetInterruptEnabledState(u32 id)
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{
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VirqState &state = GetVirqState(id);
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@ -243,6 +223,263 @@ namespace ams::hvisor {
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for (u32 dstCore: util::BitsOf{coreList}) {
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SetSgiPendingState(id, dstCore, currentCoreCtx->coreId);
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}
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}
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bool VirtualGic::ValidateGicdRegisterAccess(size_t offset, size_t sz)
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{
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// ipriorityr, itargetsr, *pendsgir are byte-accessible
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// Report a fault on accessing fields for
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if (
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!(offset >= GICDOFF(ipriorityr) && offset < GICDOFF(ipriorityr) + GicV2Distributor::maxIrqId) &&
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!(offset >= GICDOFF(itargetsr) && offset < GICDOFF(itargetsr) + GicV2Distributor::maxIrqId) &&
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!(offset >= GICDOFF(cpendsgir) && offset < GICDOFF(cpendsgir) + 16) &&
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!(offset >= GICDOFF(spendsgir) && offset < GICDOFF(spendsgir) + 16)
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) {
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return (offset & 3) == 0 && sz == 4;
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} else {
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return sz == 1 || (sz == 4 && ((offset & 3) != 0));
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}
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}
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void VirtualGic::WriteGicdRegister(u32 val, size_t offset, size_t sz)
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{
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static constexpr auto maxIrqId = GicV2Distributor::maxIrqId;
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std::scoped_lock lk{IrqManager::GetInstance().m_lock};
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switch (offset) {
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case GICDOFF(typer):
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case GICDOFF(iidr):
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case GICDOFF(icpidr2):
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case GICDOFF(itargetsr) ... GICDOFF(itargetsr) + 31:
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// Write ignored (read-only registers)
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break;
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case GICDOFF(icfgr) ... GICDOFF(icfgr) + 31/4:
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// Write ignored because of an implementation-defined choice
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break;
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case GICDOFF(igroupr) ... GICDOFF(igroupr) + maxIrqId/8:
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// Write ignored because we don't implement Group 1 here
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break;
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case GICDOFF(ispendr) ... GICDOFF(ispendr) + maxIrqId/8:
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case GICDOFF(icpendr) ... GICDOFF(icpendr) + maxIrqId/8:
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case GICDOFF(isactiver) ... GICDOFF(isactiver) + maxIrqId/8:
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case GICDOFF(icactiver) ... GICDOFF(icactiver) + maxIrqId/8:
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case GICDOFF(cpendsgir) ... GICDOFF(cpendsgir) + 15:
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case GICDOFF(spendsgir) ... GICDOFF(spendsgir) + 15:
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// Write ignored, not implemented (at least not yet, TODO)
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break;
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case GICDOFF(ctlr): {
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SetDistributorControlRegister(val);
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break;
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}
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case GICDOFF(isenabler) ... GICDOFF(isenabler) + maxIrqId/8: {
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u32 base = 8 * static_cast<u32>(offset - GICDOFF(isenabler));
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for(u32 pos: util::BitsOf{val}) {
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SetInterruptEnabledState(base + pos);
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}
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break;
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}
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case GICDOFF(icenabler) ... GICDOFF(icenabler) + maxIrqId/8: {
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u32 base = 8 * static_cast<u32>(offset - GICDOFF(icenabler));
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for(u32 pos: util::BitsOf{val}) {
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SetInterruptEnabledState(base + pos);
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}
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break;
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}
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case GICDOFF(ipriorityr) ... GICDOFF(ipriorityr) + maxIrqId: {
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u32 base = static_cast<u32>(offset - GICDOFF(ipriorityr));
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for (u32 i = 0; i < static_cast<u32>(sz); i++) {
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SetInterruptPriorityByte(base + i, static_cast<u8>(val));
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val >>= 8;
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}
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break;
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}
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case GICDOFF(itargetsr) + 32 ... GICDOFF(itargetsr) + maxIrqId: {
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u32 base = static_cast<u32>(offset - GICDOFF(itargetsr));
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for (u32 i = 0; i < static_cast<u32>(sz); i++) {
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SetInterruptTargets(base + i, static_cast<u8>(val));
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val >>= 8;
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}
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break;
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}
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case GICDOFF(icfgr) + 32/4 ... GICDOFF(icfgr) + maxIrqId/4: {
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u32 base = 4 * static_cast<u32>(offset & 0xFF);
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for (u32 i = 0; i < 16; i++) {
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SetInterruptConfigBits(base + i, val & 3);
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val >>= 2;
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}
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break;
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}
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case GICDOFF(sgir): {
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SendSgi(val & 0xF, static_cast<GicV2Distributor::SgirTargetListFilter>((val >> 24) & 3), (val >> 16) & 0xFF);
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break;
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}
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default:
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DEBUG("Write to GICD reserved/implementation-defined register offset=0x%03lx value=0x%08lx", offset, val);
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break;
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}
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UpdateState();
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}
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u32 VirtualGic::ReadGicdRegister(size_t offset, size_t sz)
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{
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static constexpr auto maxIrqId = GicV2Distributor::maxIrqId;
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std::scoped_lock lk{IrqManager::GetInstance().m_lock};
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//DEBUG("gicd read off 0x%03llx sz %lx\n", offset, sz);
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u32 val = 0;
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switch (offset) {
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case GICDOFF(icfgr) ... GICDOFF(icfgr) + 31/4:
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// RAZ because of an implementation-defined choice
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break;
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case GICDOFF(igroupr) ... GICDOFF(igroupr) + maxIrqId/8:
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// RAZ because we don't implement Group 1 here
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break;
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case GICDOFF(ispendr) ... GICDOFF(ispendr) + maxIrqId/8:
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case GICDOFF(icpendr) ... GICDOFF(icpendr) + maxIrqId/8:
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case GICDOFF(isactiver) ... GICDOFF(isactiver) + maxIrqId/8:
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case GICDOFF(icactiver) ... GICDOFF(icactiver) + maxIrqId/8:
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case GICDOFF(cpendsgir) ... GICDOFF(cpendsgir) + 15:
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case GICDOFF(spendsgir) ... GICDOFF(spendsgir) + 15:
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// RAZ, not implemented (at least not yet, TODO)
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break;
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case GICDOFF(ctlr): {
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val = GetDistributorControlRegister();
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break;
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}
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case GICDOFF(typer): {
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val = GetDistributorTypeRegister();
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break;
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}
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case GICDOFF(iidr): {
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val = GetDistributorImplementerIdentificationRegister();
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break;
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}
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case GICDOFF(isenabler) ... GICDOFF(isenabler) + maxIrqId/8:
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case GICDOFF(icenabler) ... GICDOFF(icenabler) + maxIrqId/8: {
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u32 base = 8 * static_cast<u32>(offset & 0x7F);
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for (u32 i = 0; i < 32; i++) {
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val |= GetInterruptEnabledState(base + i) ? BIT(i) : 0;
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}
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break;
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}
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case GICDOFF(ipriorityr) ... GICDOFF(ipriorityr) + maxIrqId: {
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u32 base = static_cast<u32>(offset - GICDOFF(ipriorityr));
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for (u32 i = 0; i < sz; i++) {
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val |= GetInterruptPriorityByte(base + i) << (8 * i);
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}
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break;
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}
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case GICDOFF(itargetsr) ... GICDOFF(itargetsr) + maxIrqId: {
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u32 base = static_cast<u32>(offset - GICDOFF(itargetsr));
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for (u32 i = 0; i < sz; i++) {
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val |= GetInterruptTargets(base + i) << (8 * i);
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}
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break;
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}
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case GICDOFF(icfgr) + 32/4 ... GICDOFF(icfgr) + maxIrqId/4: {
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u32 base = 4 * static_cast<u32>(offset & 0xFF);
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for (u32 i = 0; i < 16; i++) {
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val |= GetInterruptConfigBits(base + i) << (2 * i);
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}
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break;
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}
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case GICDOFF(sgir):
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// Write-only register
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DEBUG("Read from write-only register GCID_SGIR\n");
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break;
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case GICDOFF(icpidr2): {
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val = GetPeripheralId2Register();
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break;
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}
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default:
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DEBUG("Read from GICD reserved/implementation-defined register offset=0x%03lx\n", offset);
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break;
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}
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UpdateState();
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return val;
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}
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void VirtualGic::ResampleVirqLevel(VirtualGic::VirqState &state)
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{
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/*
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For hardware interrupts, we have kept the interrupt active on the physical GICD
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For level-sensitive interrupts, we need to check if they're also still physically pending (resampling).
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If not, there's nothing to service anymore, and therefore we have to deactivate them, so that
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we're notified when they become pending again.
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*/
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if (!state.levelSensitive || !state.IsPending()) {
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// Nothing to do for edge-triggered interrupts and non-pending interrupts
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return;
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}
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u32 irqId = state.irqId;
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// Can't do anything for level-sensitive PPIs from other cores either
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if (irqId < 32 && state.coreId != currentCoreCtx->coreId) {
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return;
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}
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bool lineLevel = IrqManager::IsInterruptPending(irqId);
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if (!lineLevel) {
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IrqManager::ClearInterruptActive(irqId);
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state.ClearPendingLine();
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}
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}
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void VirtualGic::CleanupPendingQueue()
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{
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// SGIs are pruned elsewhere
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// Resample line level for level-sensitive interrupts
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for (VirqState &state: m_virqPendingQueue) {
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ResampleVirqLevel(state);
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}
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// Cleanup the list
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m_virqPendingQueue.erase_if([](const VirqState &state) { return !state.IsPending(); });
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}
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size_t VirtualGic::ChoosePendingInterrupts(VirtualGic::VirqState *chosen[], size_t maxNum)
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{
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size_t numChosen = 0;
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auto pred = [](const VirqState &state) {
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if (state.irqId < 32 && state.coreId != currentCoreCtx->coreId) {
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// We can't handle SGIs/PPIs of other cores.
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return false;
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}
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return state.enabled && (state.irqId < 32 || (state.targetList & BIT(currentCoreCtx->coreId)) != 0);
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};
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for (VirqState &state: m_virqPendingQueue) {
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if (pred(state)) {
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chosen[numChosen++] = &state;
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}
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}
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for (size_t i = 0; i < numChosen; i++) {
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chosen[i]->handled = true;
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m_virqPendingQueue.erase(*chosen[i]);
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}
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}
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}
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