exo2: implement the rest of cpu suspend (security checks TODO)

This commit is contained in:
Michael Scire 2020-06-08 00:41:27 -07:00 committed by SciresM
parent 34098f7215
commit 2fb363dcf0
12 changed files with 384 additions and 8 deletions

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@ -21,7 +21,8 @@ namespace ams::pkg1 {
enum AesKeySlot {
AesKeySlot_UserStart = 0,
AesKeySlot_TzramSave = 2,
AesKeySlot_TzramSaveKek = 2,
AesKeySlot_TzramSaveKey = 3,
AesKeySlot_UserLast = 5,
AesKeySlot_UserEnd = AesKeySlot_UserLast + 1,

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@ -42,8 +42,8 @@ namespace ams::pmc {
void LockSecureRegister(SecureRegister reg);
enum class LockState {
Locked = 0,
NotLocked = 1,
Locked = 0,
NotLocked = 1,
PartiallyLocked = 2,
};

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@ -38,6 +38,9 @@ namespace ams::se {
void ComputeAes128Cmac(void *dst, size_t dst_size, int slot, const void *src, size_t src_size);
void ComputeAes256Cmac(void *dst, size_t dst_size, int slot, const void *src, size_t src_size);
void EncryptAes128Cbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size);
void EncryptAes256Cbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size);
void EncryptAes128CbcAsync(u32 out_ll_address, int slot, u32 in_ll_address, u32 size, const void *iv, size_t iv_size, DoneHandler handler);
void DecryptAes128CbcAsync(u32 out_ll_address, int slot, u32 in_ll_address, u32 size, const void *iv, size_t iv_size, DoneHandler handler);
void ComputeAes128CtrAsync(u32 out_ll_address, int slot, u32 in_ll_address, u32 size, const void *iv, size_t iv_size, DoneHandler handler);

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@ -30,6 +30,7 @@ namespace ams::se {
void HandleInterrupt();
void ValidateErrStatus();
void ValidateAesOperationResult();
}
}

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@ -51,5 +51,6 @@ namespace ams::se {
static_assert(util::is_pod<StickyBits>::value);
bool ValidateStickyBits(const StickyBits &bits);
void SaveContext(Context *dst);
}
}

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@ -61,7 +61,7 @@ DEFINE_FLOW_REG_BIT_ENUM(HALT_CPUN_EVENTS_LIC_IRQN, 11, DISABLE, ENABLE);
DEFINE_FLOW_REG_THREE_BIT_ENUM(HALT_CPUN_EVENTS_FLOW_MODE, 29, NONE, RUN_AND_INT, WAITEVENT, WAITEVENT_AND_INT, STOP_UNTIL_IRQ, STOP_UNTIL_EVENT_AND_IRQ, RESERVED6, RESERVED7);
DEFINE_FLOW_REG_BIT_ENUM(HALT_COP_EVENTS_JTAG, 28, ENABLED, DISABLED);
DEFINE_FLOW_REG_BIT_ENUM(HALT_COP_EVENTS_JTAG, 28, DISABLED, ENABLED);
DEFINE_FLOW_REG_THREE_BIT_ENUM(HALT_COP_EVENTS_MODE, 29, FLOW_MODE_NONE, FLOW_MODE_RUN_AND_INT, FLOW_MODE_STOP, FLOW_MODE_STOP_AND_INT, FLOW_MODE_STOP_UNTIL_IRQ, FLOW_MODE_STOP_UNTIL_IRQ_AND_INT, FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ, RESERVED7);
DEFINE_FLOW_REG_BIT_ENUM(FLOW_DBG_QUAL_FIQ2CCPLEX_ENABLE, 28, DISABLE, ENABLE);

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@ -185,6 +185,8 @@ DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_AUD, 27, OFF, ON);
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_DFD, 28, OFF, ON);
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VE2, 29, OFF, ON);
DEFINE_PMC_REG(PWRGATE_STATUS_CE123, 9, 3);
DEFINE_PMC_REG(SET_SW_CLAMP_CRAIL, 0, 1);
DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3);