mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-06-05 01:03:43 -04:00
exo2: implement warmboot firmware
This commit is contained in:
Michael Scire
SciresM
parent
ff87ff2592
commit
293c213bf2
43 changed files with 1996 additions and 103 deletions
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@ -109,4 +109,7 @@ namespace ams::fuse {
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int GetExpectedFuseVersion(TargetFirmware target_fw);
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bool HasRcmVulnerabilityPatch();
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bool IsOdmProductionMode();
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void ConfigureFuseBypass();
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}
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@ -27,6 +27,7 @@ namespace ams::pmic {
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Regulator_Mariko_Max77812_B = 2, /* Device code 0x3A000006 */
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};
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void SetEnBit(Regulator regulator);
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void EnableVddCpu(Regulator regulator);
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void DisableVddCpu(Regulator regulator);
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void EnableSleep();
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@ -87,6 +87,10 @@ namespace ams::reg {
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template<typename... Values> requires ((sizeof...(Values) > 0) && (std::is_same<Values, BitsValue>::value && ...))
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ALWAYS_INLINE bool HasValue(uintptr_t reg, const Values... values) { return Read(reg, (EncodeMask(values) | ...)) == Encode(values...); }
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ALWAYS_INLINE u32 GetValue(volatile u32 *reg, const BitsMask mask) { return Read(reg, mask) >> GetOffset(mask); }
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ALWAYS_INLINE u32 GetValue(volatile u32 ®, const BitsMask mask) { return Read(reg, mask) >> GetOffset(mask); }
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ALWAYS_INLINE u32 GetValue(uintptr_t reg, const BitsMask mask) { return Read(reg, mask) >> GetOffset(mask); }
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ALWAYS_INLINE void ReadWrite(volatile u32 *reg, u32 val, u32 mask) { *reg = (*reg & (~mask)) | (val & mask); }
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ALWAYS_INLINE void ReadWrite(volatile u32 ®, u32 val, u32 mask) { reg = ( reg & (~mask)) | (val & mask); }
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ALWAYS_INLINE void ReadWrite(uintptr_t reg, u32 val, u32 mask) { ReadWrite(reinterpret_cast<volatile u32 *>(reg), val, mask); }
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@ -23,6 +23,7 @@ namespace ams::se {
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constexpr inline size_t AesBlockSize = crypto::AesEncryptor128::BlockSize;
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void ClearAesKeySlot(int slot);
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void ClearAesKeyIv(int slot);
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void LockAesKeySlot(int slot, u32 flags);
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void SetAesKey(int slot, const void *key, size_t key_size);
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@ -40,6 +41,8 @@ namespace ams::se {
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void EncryptAes128Cbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size);
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void EncryptAes256Cbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size);
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void DecryptAes128Cbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size);
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void DecryptAes256Cbc(void *dst, size_t dst_size, int slot, const void *src, size_t src_size, const void *iv, size_t iv_size);
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void EncryptAes128CbcAsync(u32 out_ll_address, int slot, u32 in_ll_address, u32 size, const void *iv, size_t iv_size, DoneHandler handler);
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void DecryptAes128CbcAsync(u32 out_ll_address, int slot, u32 in_ll_address, u32 size, const void *iv, size_t iv_size, DoneHandler handler);
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@ -26,6 +26,8 @@
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#include <exosphere/tegra/tegra_ictlr.hpp>
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#include <exosphere/tegra/tegra_mc.hpp>
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#include <exosphere/tegra/tegra_mselect.hpp>
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#include <exosphere/tegra/tegra_pinmux.hpp>
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#include <exosphere/tegra/tegra_pg_up.hpp>
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#include <exosphere/tegra/tegra_pmc.hpp>
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#include <exosphere/tegra/tegra_sb.hpp>
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#include <exosphere/tegra/tegra_sysctr0.hpp>
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@ -16,22 +16,32 @@
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#pragma once
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#include <vapours.hpp>
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#define APB_MISC_PP_CONFIG_CTL (0x024)
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#define APB_MISC_GP_ASDBGREG (0x810)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 (0xc04)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 (0xc08)
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#define AHB_MISC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (AHB_MISC, NAME)
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#define AHB_MISC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (AHB_MISC, NAME, VALUE)
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#define AHB_MISC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (AHB_MISC, NAME, ENUM)
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#define AHB_MISC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(AHB_MISC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
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#define APB_MISC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (APB_MISC, NAME)
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#define APB_MISC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (APB_MISC, NAME, VALUE)
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#define APB_MISC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (APB_MISC, NAME, ENUM)
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#define APB_MISC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(APB_MISC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
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#define DEFINE_AHB_MISC_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (AHB_MISC, NAME, __OFFSET__, __WIDTH__)
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#define DEFINE_AHB_MISC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (AHB_MISC, NAME, __OFFSET__, ZERO, ONE)
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#define DEFINE_AHB_MISC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (AHB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
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#define DEFINE_AHB_MISC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(AHB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
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#define DEFINE_AHB_MISC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (AHB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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#define DEFINE_APB_MISC_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (APB_MISC, NAME, __OFFSET__, __WIDTH__)
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#define DEFINE_APB_MISC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (APB_MISC, NAME, __OFFSET__, ZERO, ONE)
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#define DEFINE_APB_MISC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (APB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
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#define DEFINE_APB_MISC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(APB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
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#define DEFINE_APB_MISC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (APB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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#define DEFINE_SLAVE_SECURITY_REG(RINDEX, INDEX, NAME) DEFINE_AHB_MISC_REG_BIT_ENUM(SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG##RINDEX##_##NAME##_SECURITY_EN, INDEX, DISABLE, ENABLE)
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DEFINE_APB_MISC_REG_BIT_ENUM(PP_CONFIG_CTL_JTAG, 6, DISABLE, ENABLE);
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DEFINE_APB_MISC_REG_BIT_ENUM(PP_CONFIG_CTL_TBE, 7, DISABLE, ENABLE);
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DEFINE_APB_MISC_REG(GP_ASDBGREG_CFG2TMC_RAM_SVOP_PDP, 24, 2);
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#define DEFINE_SLAVE_SECURITY_REG(RINDEX, INDEX, NAME) DEFINE_APB_MISC_REG_BIT_ENUM(SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG##RINDEX##_##NAME##_SECURITY_EN, INDEX, DISABLE, ENABLE)
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DEFINE_SLAVE_SECURITY_REG(0, 29, STM);
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DEFINE_SLAVE_SECURITY_REG(0, 24, CEC);
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@ -96,4 +106,4 @@ DEFINE_SLAVE_SECURITY_REG(2, 0, SDMMC1);
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#undef DEFINE_SLAVE_SECURITY_REG
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#define SLAVE_SECURITY_REG_BITS_ENUM(RINDEX, NAME, ENUM) AHB_MISC_REG_BITS_ENUM(SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG##RINDEX##_##NAME##_SECURITY_EN, ENUM)
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#define SLAVE_SECURITY_REG_BITS_ENUM(RINDEX, NAME, ENUM) APB_MISC_REG_BITS_ENUM(SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG##RINDEX##_##NAME##_SECURITY_EN, ENUM)
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@ -29,14 +29,51 @@
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#define DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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#define CLK_RST_CONTROLLER_RST_SOURCE (0x000)
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#define CLK_RST_CONTROLLER_RST_SOURCE (0x000)
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048)
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048)
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#define CLK_RST_CONTROLLER_OSC_CTRL (0x050)
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#define CLK_RST_CONTROLLER_PLLX_BASE (0x0E0)
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#define CLK_RST_CONTROLLER_CCLKG_BURST_POLICY (0x368)
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#define CLK_RST_CONTROLLER_SUPER_CCLKG_DIVIDER (0x36C)
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#define CLK_RST_CONTROLLER_CCLKLP_BURST_POLICY (0x370)
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#define CLK_RST_CONTROLLER_SUPER_CCLKLP_DIVIDER (0x374)
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#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 (0x388)
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#define CLK_RST_CONTROLLER_SPARE_REG0 (0x55C)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA (0x0F8)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB (0x0FC)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC (0x3A0)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD (0x3A4)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE (0x554)
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DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
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DEFINE_CLK_RST_REG_BIT_ENUM(OSC_CTRL_XOE, 0, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(OSC_CTRL_XOFS, 4, 6);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_BASE_PLLX_ENABLE, 30, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVISOR, 0, 8);
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DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVIDEND, 8, 8);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_CPU_IRQ, 24, NO_IMPACT, DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_COP_IRQ, 25, NO_IMPACT, DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_CPU_FIQ, 26, NO_IMPACT, DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_COP_FIQ, 27, NO_IMPACT, DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLKG_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLKLP_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_IDLE_SOURCE, 0, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_RUN_SOURCE, 4, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_IRQ_SOURCE, 8, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_FIQ_SOURCE, 12, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CPU_STATE, 28, STDBY, IDLE, RUN, RSVD3, IRQ, RSVD5, RSVD6, RSVD7, FIQ, RSVD9, RSVD10, RSVD11, RSVD12, RSVD13, RSVD14, RSVD15);
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DEFINE_CLK_RST_REG(CPU_SOFTRST_CTRL2_CAR2PMC_CPU_ACK_WIDTH, 0, 12);
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DEFINE_CLK_RST_REG_TWO_BIT_ENUM(SPARE_REG0_CLK_M_DIVISOR, 2, CLK_M_DIVISOR1, CLK_M_DIVISOR2, CLK_M_DIVISOR3, CLK_M_DIVISOR4);
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/* RST_DEVICES */
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#define CLK_RST_CONTROLLER_RST_DEVICES_L (0x004)
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#define CLK_RST_CONTROLLER_RST_DEVICES_H (0x008)
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@ -56,18 +93,45 @@ DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W (0x364)
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/* CLK_SOURCE */
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 (0x124)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 (0x128)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 (0x124)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 (0x128)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT (0x3B4)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF (0x62C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC (0x630)
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/* RST_DEV_*_SET */
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#define CLK_RST_CONTROLLER_RST_DEV_L_SET (0x300)
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#define CLK_RST_CONTROLLER_RST_DEV_H_SET (0x308)
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#define CLK_RST_CONTROLLER_RST_DEV_U_SET (0x310)
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#define CLK_RST_CONTROLLER_RST_DEV_V_SET (0x430)
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/* RST_DEV_*_CLR */
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#define CLK_RST_CONTROLLER_RST_DEV_L_CLR (0x304)
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#define CLK_RST_CONTROLLER_RST_DEV_H_CLR (0x30C)
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#define CLK_RST_CONTROLLER_RST_DEV_U_CLR (0x314)
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#define CLK_RST_CONTROLLER_RST_DEV_V_CLR (0x434)
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/* CLK_ENB_*_SET */
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#define CLK_RST_CONTROLLER_CLK_ENB_L_SET (0x320)
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#define CLK_RST_CONTROLLER_CLK_ENB_H_SET (0x328)
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#define CLK_RST_CONTROLLER_CLK_ENB_U_SET (0x330)
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET (0x440)
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET (0x448)
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET (0x284)
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#define CLK_RST_CONTROLLER_CLK_ENB_Y_SET (0x29C)
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/* CLK_ENB_*_CLR */
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#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR (0x324)
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#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR (0x32C)
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#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR (0x334)
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#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR (0x288)
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#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR (0x2A0)
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#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR (0x444)
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#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR (0x44C)
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/* CLK_ENB_*_INDEX */
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#define CLK_RST_CONTROLLER_CLK_ENB_I2C1_INDEX (0x0C)
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@ -95,14 +159,92 @@ DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC3_LEGACY_TMCLK_OVR_ON, 30, O
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC4_LEGACY_TMCLK_OVR_ON, 31, OFF, ON);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_I2C1_I2C1_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG(CLK_SOURCE_I2C1_I2C1_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_I2C5_I2C5_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_I2C5_I2C5_CLK_DIVISOR, 0, 8);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTA_UARTA_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTB_UARTB_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_MSELECT_MSELECT_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT2, PLLC4_OUT1, CLK_S, CLK_M, PLLC4_OUT0);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_MSELECT_MSELECT_CLK_DIVISOR, 0, 8);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_REF_DVFS_REF_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_REF_DVFS_REF_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_SOC_DVFS_SOC_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_SOC_DVFS_SOC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_SET_SET_COP_RST, 1, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_CLR_CLR_COP_RST, 1, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET0, 0, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET1, 1, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET2, 2, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET3, 3, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET0, 16, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET1, 17, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET2, 18, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET3, 19, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENABLE);
|
||||
|
||||
/* TODO: Actually include all devices. */
|
||||
#define CLK_RST_FOREACH_DEVICE(HANDLER) \
|
||||
HANDLER(L, CPU, 0, 0) \
|
||||
HANDLER(L, RTC, 0, 4) \
|
||||
HANDLER(L, TMR, 0, 5) \
|
||||
HANDLER(L, GPIO, 0, 8) \
|
||||
HANDLER(L, CACHE2, 0, 31) \
|
||||
HANDLER(H, MEM, 1, 0) \
|
||||
HANDLER(H, PMC, 1, 6) \
|
||||
HANDLER(H, FUSE, 1, 7) \
|
||||
HANDLER(H, I2C5, 1, 15) \
|
||||
HANDLER(H, EMC, 1, 25) \
|
||||
HANDLER(U, CSITE, 2, 9) \
|
||||
HANDLER(U, IRAMA, 2, 20) \
|
||||
HANDLER(U, IRAMB, 2, 21) \
|
||||
HANDLER(U, IRAMC, 2, 22) \
|
||||
HANDLER(U, IRAMD, 2, 23) \
|
||||
HANDLER(U, CRAM2, 2, 24) \
|
||||
HANDLER(V, CPUG, 3, 0) \
|
||||
HANDLER(V, MSELECT, 3, 3) \
|
||||
HANDLER(V, SPDIF_DOUBLER, 3, 22) \
|
||||
HANDLER(V, TZRAM, 3, 30) \
|
||||
HANDLER(V, SE, 3, 31) \
|
||||
HANDLER(W, PCIERX0, 4, 2) \
|
||||
HANDLER(W, PCIERX1, 4, 3) \
|
||||
HANDLER(W, PCIERX2, 4, 4) \
|
||||
HANDLER(W, PCIERX3, 4, 5) \
|
||||
HANDLER(W, PCIERX4, 4, 6) \
|
||||
HANDLER(W, PCIERX5, 4, 7) \
|
||||
HANDLER(W, ENTROPY, 4, 21) \
|
||||
HANDLER(W, DVFS, 4, 27) \
|
||||
HANDLER(W, MC1, 4, 30) \
|
||||
HANDLER(X, MC_CAPA, 5, 7) \
|
||||
HANDLER(X, MC_CBPA, 5, 8) \
|
||||
HANDLER(X, MC_CPU, 5, 9) \
|
||||
HANDLER(X, MC_BBC, 5, 10) \
|
||||
HANDLER(X, EMC_DLL, 5, 14) \
|
||||
HANDLER(X, GPU, 5, 24) \
|
||||
HANDLER(X, DBGAPB, 5, 25) \
|
||||
HANDLER(X, PLLG_REF, 5, 29) \
|
||||
HANDLER(Y, MC_CCPA, 6, 8) \
|
||||
HANDLER(Y, MC_CDPA, 6, 9) \
|
||||
HANDLER(Y, PLLP_OUT_CPU, 6, 31)
|
||||
|
||||
#define CLK_RST_DEFINE_SET_CLR_REG(REGISTER, DEVICE, REGISTER_INDEX, DEVICE_INDEX) \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_SET_SET_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_CLR_CLR_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_SET_SET_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_CLR_CLR_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE);
|
||||
|
||||
CLK_RST_FOREACH_DEVICE(CLK_RST_DEFINE_SET_CLR_REG)
|
||||
|
||||
#undef CLK_RST_DEFINE_SET_CLR_REG
|
||||
|
||||
|
|
|
|||
|
|
@ -20,20 +20,23 @@
|
|||
#define EMC0_ADDRESS(x) (0x7001E000 + x)
|
||||
#define EMC1_ADDRESS(x) (0x7001F000 + x)
|
||||
|
||||
#define EMC_CFG (0x00C)
|
||||
#define EMC_ADR_CFG (0x010)
|
||||
#define EMC_TIMING_CONTROL (0x028)
|
||||
#define EMC_SELF_REF (0x0E0)
|
||||
#define EMC_MRW (0x0E8)
|
||||
#define EMC_FBIO_CFG5 (0x104)
|
||||
#define EMC_MRW3 (0x138)
|
||||
#define EMC_AUTO_CAL_CONFIG (0x2A4)
|
||||
#define EMC_REQ_CTRL (0x2B0)
|
||||
#define EMC_EMC_STATUS (0x2B4)
|
||||
#define EMC_CFG_DIG_DLL (0x2BC)
|
||||
#define EMC_ZCAL_INTERVAL (0x2E0)
|
||||
#define EMC_PMC_SCRATCH3 (0x448)
|
||||
#define EMC_FBIO_CFG7 (0x584)
|
||||
#define EMC_CFG (0x00C)
|
||||
#define EMC_ADR_CFG (0x010)
|
||||
#define EMC_TIMING_CONTROL (0x028)
|
||||
#define EMC_SELF_REF (0x0E0)
|
||||
#define EMC_MRW (0x0E8)
|
||||
#define EMC_FBIO_CFG5 (0x104)
|
||||
#define EMC_MRW3 (0x138)
|
||||
#define EMC_AUTO_CAL_CONFIG (0x2A4)
|
||||
#define EMC_REQ_CTRL (0x2B0)
|
||||
#define EMC_EMC_STATUS (0x2B4)
|
||||
#define EMC_CFG_DIG_DLL (0x2BC)
|
||||
#define EMC_ZCAL_INTERVAL (0x2E0)
|
||||
#define EMC_PMC_SCRATCH3 (0x448)
|
||||
#define EMC_FBIO_CFG7 (0x584)
|
||||
#define EMC_PMACRO_CFG_PM_GLOBAL_0 (0xC30)
|
||||
#define EMC_PMACRO_TRAINING_CTRL_0 (0xCF8)
|
||||
#define EMC_PMACRO_TRAINING_CTRL_1 (0xCFC)
|
||||
|
||||
#define EMC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (EMC, NAME)
|
||||
#define EMC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (EMC, NAME, VALUE)
|
||||
|
|
@ -88,3 +91,27 @@ DEFINE_EMC_REG_BIT_ENUM(PMC_SCRATCH3_WEAK_BIAS, 30, DISABLED, ENABLED);
|
|||
|
||||
DEFINE_EMC_REG_BIT_ENUM(FBIO_CFG7_CH1_ENABLE, 2, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0, 16, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1, 17, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2, 18, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3, 19, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4, 20, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5, 21, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6, 22, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7, 23, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD0, 24, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD1, 25, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD2, 26, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD3, 27, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_ENABLED, 0, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_TRAIN_QPOP, 1, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_RX_E_DIRECT_ZI, 2, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR, 3, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_DRV_DQS, 4, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_ENABLED, 0, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_TRAIN_QPOP, 1, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_RX_E_DIRECT_ZI, 2, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR, 3, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_DRV_DQS, 4, DISABLED, ENABLED);
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
#pragma once
|
||||
#include <vapours.hpp>
|
||||
|
||||
|
||||
#define FLOW_CTLR_RAM_REPAIR (0x040)
|
||||
#define FLOW_CTLR_FLOW_DBG_QUAL (0x050)
|
||||
#define FLOW_CTLR_L2FLUSH_CONTROL (0x094)
|
||||
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL (0x098)
|
||||
|
|
@ -66,6 +66,9 @@ DEFINE_FLOW_REG_THREE_BIT_ENUM(HALT_COP_EVENTS_MODE, 29, FLOW_MODE_NONE, FLOW_MO
|
|||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(FLOW_DBG_QUAL_FIQ2CCPLEX_ENABLE, 28, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(RAM_REPAIR_REQ, 0, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(RAM_REPAIR_STS, 1, REQUESTED, DONE);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER, 0, FAST, SLOW);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_CLUSTER_SWITCH_ENABLE, 1, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER_LOCK, 2, DISABLE, ENABLE);
|
||||
|
|
|
|||
|
|
@ -20,3 +20,20 @@
|
|||
|
||||
#define MSELECT_CONFIG (0x000)
|
||||
|
||||
#define MSELECT_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (MSELECT, NAME)
|
||||
#define MSELECT_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (MSELECT, NAME, VALUE)
|
||||
#define MSELECT_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (MSELECT, NAME, ENUM)
|
||||
#define MSELECT_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(MSELECT, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_MSELECT_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (MSELECT, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_MSELECT_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (MSELECT, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_MSELECT_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (MSELECT, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_MSELECT_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(MSELECT, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_MSELECT_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (MSELECT, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_ERR_RESP_EN_SLAVE1, 24, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_ERR_RESP_EN_SLAVE2, 25, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE0, 27, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE1, 28, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE2, 29, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE3, 30, DISABLE, ENABLE);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours.hpp>
|
||||
|
||||
#define PG_UP(x) (0x60000000 + x)
|
||||
|
||||
#define PG_UP_TAG (0x000)
|
||||
|
||||
#define PG_UP_TAG_PID_COP 0xAAAAAAAA
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours.hpp>
|
||||
|
||||
#define PINMUX_AUX_GEN1_I2C_SCL (0x30BC)
|
||||
#define PINMUX_AUX_GEN1_I2C_SDA (0x30C0)
|
||||
#define PINMUX_AUX_PWR_I2C_SCL (0x30DC)
|
||||
#define PINMUX_AUX_PWR_I2C_SDA (0x30E0)
|
||||
|
||||
#define PINMUX_AUX_UART1_TX (0x30E4)
|
||||
#define PINMUX_AUX_UART1_RX (0x30E8)
|
||||
#define PINMUX_AUX_UART1_RTS (0x30EC)
|
||||
#define PINMUX_AUX_UART1_CTS (0x30F0)
|
||||
#define PINMUX_AUX_UART2_TX (0x30F4)
|
||||
#define PINMUX_AUX_UART2_RX (0x30F8)
|
||||
#define PINMUX_AUX_UART2_RTS (0x30FC)
|
||||
#define PINMUX_AUX_UART2_CTS (0x3100)
|
||||
#define PINMUX_AUX_UART3_TX (0x3104)
|
||||
#define PINMUX_AUX_UART3_RX (0x3108)
|
||||
#define PINMUX_AUX_UART3_RTS (0x310C)
|
||||
#define PINMUX_AUX_UART3_CTS (0x3110)
|
||||
#define PINMUX_AUX_DVFS_PWM (0x3184)
|
||||
#define PINMUX_AUX_GPIO_PA6 (0x3244)
|
||||
|
||||
#define PINMUX_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (PINMUX, NAME)
|
||||
#define PINMUX_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (PINMUX, NAME, VALUE)
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#define PINMUX_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (PINMUX, NAME, ENUM)
|
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#define PINMUX_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(PINMUX, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
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#define DEFINE_PINMUX_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (PINMUX, NAME, __OFFSET__, __WIDTH__)
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#define DEFINE_PINMUX_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (PINMUX, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_PINMUX_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (PINMUX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_PINMUX_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(PINMUX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_PINMUX_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (PINMUX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_PUPD, 2, NONE, PULL_DOWN, PULL_UP, RSVD);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_TRISTATE, 4, PASSTHROUGH, TRISTATE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_PARK, 5, NORMAL, PARKED);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_INPUT, 6, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_LOCK, 7, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_LPDR, 8, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_OD, 11, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_SCHMT, 12, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GEN1_I2C_PM, 0, I2C1, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_PWR_I2C_PM, 0, I2CPMU, RSVD1, RSVD2, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_UART1_PM, 0, UARTA, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_UART2_PM, 0, UARTB, I2S4A, RSVD2, UART);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_UART3_PM, 0, UARTC, SPI4, RSVD2, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_DVFS_PWM_PM, 0, RSVD0, CLDVFS, SPI3, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GPIO_PA6_PM, 0, SATA, RSVD1, RSVD2, RSVD3);
|
||||
|
|
@ -50,6 +50,7 @@
|
|||
#define APBDEV_PMC_WAKE2_LVL (0x164)
|
||||
#define APBDEV_PMC_WAKE2_STATUS (0x168)
|
||||
#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170)
|
||||
#define APBDEV_PMC_OSC_EDPD_OVER (0x1A4)
|
||||
#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8)
|
||||
#define APBDEV_PMC_IO_DPD_REQ (0x1B8)
|
||||
#define APBDEV_PMC_IO_DPD_STATUS (0x1BC)
|
||||
|
|
@ -59,6 +60,7 @@
|
|||
#define APBDEV_PMC_SCRATCH45 (0x234)
|
||||
#define APBDEV_PMC_SCRATCH46 (0x238)
|
||||
#define APBDEV_PMC_TSC_MULT (0x2B4)
|
||||
#define APBDEV_PMC_STICKY_BITS (0x2C0)
|
||||
#define APBDEV_PMC_WEAK_BIAS (0x2C8)
|
||||
#define APBDEV_PMC_GPU_RG_CNTRL (0x2D4)
|
||||
#define APBDEV_PMC_CNTRL2 (0x440)
|
||||
|
|
@ -162,6 +164,8 @@ enum APBDEV_PMC_PWRGATE_TOGGLE_PARTID : u8 {
|
|||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VE2 = 29,
|
||||
};
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(REMOVE_CLAMPING_COMMAND_CRAIL, 0, DISABLE, ENABLE);
|
||||
|
||||
enum APBDEV_PMC_PWRGATE_STATUS_STATUS {
|
||||
APBDEV_PMC_PWRGATE_STATUS_STATUS_OFF = 0,
|
||||
APBDEV_PMC_PWRGATE_STATUS_STATUS_ON = 1,
|
||||
|
|
@ -221,4 +225,11 @@ DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBC, 22, DISABLE, ENABLE);
|
|||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VIC, 23, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_IRAM, 24, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG(OSC_EDPD_OVER_XOFS, 1, 6);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(STICKY_BITS_HDA_LPBK_DIS, 0, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(STICKY_BITS_JTAG_STS, 6, ENABLE, DISABLE);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(CNTRL2_WAKE_DET_EN, 9, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(SEC_DISABLE2_WRITE21, 26, OFF, ON);
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <vapours.hpp>
|
||||
|
||||
#define SB_CSR (0x200)
|
||||
#define SB_PFCFG (0x208)
|
||||
#define SB_AA64_RESET_LOW (0x230)
|
||||
#define SB_AA64_RESET_HIGH (0x234)
|
||||
|
||||
|
|
@ -39,3 +40,8 @@ DEFINE_SB_REG_BIT_ENUM(CSR_HANG, 6, DISABLE, ENABLE);
|
|||
DEFINE_SB_REG_BIT_ENUM(CSR_SWDM_ENABLE, 7, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG(CSR_SWDM_FAIL_COUNT, 8, 4);
|
||||
DEFINE_SB_REG(CSR_COT_FAIL_COUNT, 12, 4);
|
||||
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_SPNIDEN, 0, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_SPIDEN, 1, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_NIDEN, 2, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_DBGEN, 3, DISABLE, ENABLE);
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
#pragma once
|
||||
#include <vapours.hpp>
|
||||
|
||||
|
||||
#define TIMERUS_USEC_CFG (0x014)
|
||||
#define TIMER_SHARED_TIMER_SECURE_CFG (0x1A4)
|
||||
|
||||
#define TIMER_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (TIMER, NAME)
|
||||
|
|
@ -30,6 +30,9 @@
|
|||
#define DEFINE_TIMER_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_TIMER_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_TIMER_REG(USEC_CFG_USEC_DIVISOR, 0, 8);
|
||||
DEFINE_TIMER_REG(USEC_CFG_USEC_DIVIDEND, 8, 8);
|
||||
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR5, 5, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR6, 6, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR7, 7, DISABLE, ENABLE);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue