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boot: refactor to use sts::boot namespace

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This commit is contained in:
Michael Scire 2019-06-22 00:10:21 -07:00
parent 4fbae9e5a4
commit 06416aeded
91 changed files with 3665 additions and 3155 deletions
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136
stratosphere/boot/source/boot_wake_pins.cpp
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@ -14,75 +14,99 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "boot_functions.hpp"
#include "boot_pmc_wrapper.hpp"
#include "boot_spl_utils.hpp"
#include "boot_wake_pins.hpp"
#include "boot_registers_pmc.hpp"
#include "boot_wake_control_configs.hpp"
#include "boot_wake_pin_configuration.hpp"
#include "boot_wake_pin_configuration_copper.hpp"
static void UpdatePmcControlBit(const u32 reg_offset, const u32 mask_val, const bool flag) {
Boot::WritePmcRegister(PmcBase + reg_offset, flag ? UINT32_MAX : 0, mask_val);
Boot::ReadPmcRegister(PmcBase + reg_offset);
}
namespace sts::boot {
static void InitializePmcWakeConfiguration(const bool is_blink) {
/* Initialize APBDEV_PMC_WAKE_DEBOUNCE_EN, do a dummy read. */
Boot::WritePmcRegister(PmcBase + APBDEV_PMC_WAKE_DEBOUNCE_EN, 0);
Boot::ReadPmcRegister(PmcBase + APBDEV_PMC_WAKE_DEBOUNCE_EN);
/* Include configuration into anonymous namespace. */
namespace {
/* Initialize APBDEV_PMC_BLINK_TIMER, do a dummy read. */
Boot::WritePmcRegister(PmcBase + APBDEV_PMC_BLINK_TIMER, 0x8008800);
Boot::ReadPmcRegister(PmcBase + APBDEV_PMC_BLINK_TIMER);
struct WakePinConfig {
u32 index;
bool enabled;
u32 level;
};
#include "boot_wake_control_configs.inc"
#include "boot_wake_pin_configuration.inc"
#include "boot_wake_pin_configuration_copper.inc"
/* Set control bits, do dummy reads. */
for (size_t i = 0; i < NumWakeControlConfigs; i++) {
UpdatePmcControlBit(WakeControlConfigs[i].reg_offset, WakeControlConfigs[i].mask_val, WakeControlConfigs[i].flag_val);
}
/* Set bit 0x80 in APBDEV_PMC_CNTRL based on is_blink, do dummy read. */
UpdatePmcControlBit(APBDEV_PMC_CNTRL, 0x80, is_blink);
namespace {
/* Set bit 0x100000 in APBDEV_PMC_DPD_PADS_ORIDE based on is_blink, do dummy read. */
UpdatePmcControlBit(APBDEV_PMC_DPD_PADS_ORIDE, 0x100000, is_blink);
}
/* Helpers. */
void UpdatePmcControlBit(const u32 reg_offset, const u32 mask_val, const bool flag) {
WritePmcRegister(PmcBase + reg_offset, flag ? UINT32_MAX : 0, mask_val);
ReadPmcRegister(PmcBase + reg_offset);
}
void InitializePmcWakeConfiguration(const bool is_blink) {
/* Initialize APBDEV_PMC_WAKE_DEBOUNCE_EN, do a dummy read. */
WritePmcRegister(PmcBase + APBDEV_PMC_WAKE_DEBOUNCE_EN, 0);
ReadPmcRegister(PmcBase + APBDEV_PMC_WAKE_DEBOUNCE_EN);
/* Initialize APBDEV_PMC_BLINK_TIMER, do a dummy read. */
WritePmcRegister(PmcBase + APBDEV_PMC_BLINK_TIMER, 0x8008800);
ReadPmcRegister(PmcBase + APBDEV_PMC_BLINK_TIMER);
/* Set control bits, do dummy reads. */
for (size_t i = 0; i < NumWakeControlConfigs; i++) {
UpdatePmcControlBit(WakeControlConfigs[i].reg_offset, WakeControlConfigs[i].mask_val, WakeControlConfigs[i].flag_val);
}
/* Set bit 0x80 in APBDEV_PMC_CNTRL based on is_blink, do dummy read. */
UpdatePmcControlBit(APBDEV_PMC_CNTRL, 0x80, is_blink);
/* Set bit 0x100000 in APBDEV_PMC_DPD_PADS_ORIDE based on is_blink, do dummy read. */
UpdatePmcControlBit(APBDEV_PMC_DPD_PADS_ORIDE, 0x100000, is_blink);
}
void SetWakeEventLevel(u32 index, u32 level) {
u32 pmc_wake_level_reg_offset = index <= 0x1F ? APBDEV_PMC_WAKE_LVL : APBDEV_PMC_WAKE2_LVL;
u32 pmc_wake_level_mask_reg_offset = index <= 0x1F ? APBDEV_PMC_AUTO_WAKE_LVL_MASK : APBDEV_PMC_AUTO_WAKE2_LVL_MASK;
if (level != 2) {
std::swap(pmc_wake_level_reg_offset, pmc_wake_level_mask_reg_offset);
}
const u32 mask_val = (1 << (index & 0x1F));
/* Clear level reg bit. */
UpdatePmcControlBit(pmc_wake_level_reg_offset, mask_val, false);
/* Set or clear mask reg bit. */
UpdatePmcControlBit(pmc_wake_level_mask_reg_offset, mask_val, level > 0);
}
void SetWakeEventEnabled(u32 index, bool enabled) {
/* Set or clear enabled bit. */
UpdatePmcControlBit(index <= 0x1F ? APBDEV_PMC_WAKE_MASK : APBDEV_PMC_WAKE2_MASK, (1 << (index & 0x1F)), enabled);
}
void Boot::SetWakeEventLevel(u32 index, u32 level) {
u32 pmc_wake_level_reg_offset = index <= 0x1F ? APBDEV_PMC_WAKE_LVL : APBDEV_PMC_WAKE2_LVL;
u32 pmc_wake_level_mask_reg_offset = index <= 0x1F ? APBDEV_PMC_AUTO_WAKE_LVL_MASK : APBDEV_PMC_AUTO_WAKE2_LVL_MASK;
if (level != 2) {
std::swap(pmc_wake_level_reg_offset, pmc_wake_level_mask_reg_offset);
}
const u32 mask_val = (1 << (index & 0x1F));
void SetInitialWakePinConfiguration() {
InitializePmcWakeConfiguration(false);
/* Clear level reg bit. */
UpdatePmcControlBit(pmc_wake_level_reg_offset, mask_val, false);
/* Set wake event levels, wake event enables. */
const WakePinConfig *configs;
size_t num_configs;
if (GetHardwareType() == spl::HardwareType::Copper) {
configs = WakePinConfigsCopper;
num_configs = NumWakePinConfigsCopper;
} else {
configs = WakePinConfigs;
num_configs = NumWakePinConfigs;
}
/* Set or clear mask reg bit. */
UpdatePmcControlBit(pmc_wake_level_mask_reg_offset, mask_val, level > 0);
}
void Boot::SetWakeEventEnabled(u32 index, bool enabled) {
/* Set or clear enabled bit. */
UpdatePmcControlBit(index <= 0x1F ? APBDEV_PMC_WAKE_MASK : APBDEV_PMC_WAKE2_MASK, (1 << (index & 0x1F)), enabled);
}
void Boot::SetInitialWakePinConfiguration() {
InitializePmcWakeConfiguration(false);
/* Set wake event levels, wake event enables. */
const WakePinConfig *configs;
size_t num_configs;
if (Boot::GetHardwareType() == HardwareType_Copper) {
configs = WakePinConfigsCopper;
num_configs = NumWakePinConfigsCopper;
} else {
configs = WakePinConfigs;
num_configs = NumWakePinConfigs;
for (size_t i = 0; i < num_configs; i++) {
SetWakeEventLevel(configs[i].index, configs[i].level);
SetWakeEventEnabled(configs[i].index, configs[i].enabled);
}
}
for (size_t i = 0; i < num_configs; i++) {
Boot::SetWakeEventLevel(configs[i].index, configs[i].level);
Boot::SetWakeEventEnabled(configs[i].index, configs[i].enabled);
}
}